By Topic

Date 24-27 Nov. 2008

Filter Results

Displaying Results 1 - 25 of 96
  • [Front cover]

    Publication Year: 2008
    Request permission for commercial reuse | PDF file iconPDF (324 KB)
    Freely Available from IEEE
  • [Title page i]

    Publication Year: 2008, Page(s): i
    Request permission for commercial reuse | PDF file iconPDF (26 KB)
    Freely Available from IEEE
  • [Title page iii]

    Publication Year: 2008, Page(s): iii
    Request permission for commercial reuse | PDF file iconPDF (88 KB)
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2008, Page(s): iv
    Request permission for commercial reuse | PDF file iconPDF (44 KB)
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2008, Page(s):v - xi
    Request permission for commercial reuse | PDF file iconPDF (134 KB)
    Freely Available from IEEE
  • Foreword

    Publication Year: 2008, Page(s): xii
    Request permission for commercial reuse | PDF file iconPDF (102 KB) | HTML iconHTML
    Freely Available from IEEE
  • ATS Steering Committee

    Publication Year: 2008, Page(s): xiii
    Request permission for commercial reuse | PDF file iconPDF (104 KB) | HTML iconHTML
    Freely Available from IEEE
  • Organizing Committee

    Publication Year: 2008, Page(s): xiv
    Request permission for commercial reuse | PDF file iconPDF (112 KB)
    Freely Available from IEEE
  • Program Committee

    Publication Year: 2008, Page(s):xv - xvi
    Request permission for commercial reuse | PDF file iconPDF (124 KB)
    Freely Available from IEEE
  • Reviewers

    Publication Year: 2008, Page(s): xvii
    Request permission for commercial reuse | PDF file iconPDF (81 KB)
    Freely Available from IEEE
  • TTTC Activities Board

    Publication Year: 2008, Page(s):xviii - xx
    Request permission for commercial reuse | PDF file iconPDF (180 KB)
    Freely Available from IEEE
  • Tutorial 1

    Publication Year: 2008, Page(s): xxi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (112 KB)

    Provides an abstract of the tutorial presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Tutorial 2

    Publication Year: 2008, Page(s): xxii
    Request permission for commercial reuse | PDF file iconPDF (108 KB)
    Freely Available from IEEE
  • ATS 2007 Best Paper Award

    Publication Year: 2008, Page(s): xxiii
    Request permission for commercial reuse | PDF file iconPDF (123 KB) | HTML iconHTML
    Freely Available from IEEE
  • Not All Xs are Bad for Scan Compression

    Publication Year: 2008, Page(s):7 - 12
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (350 KB) | HTML iconHTML

    Scan compression technology combines the expected responses from multiple scan chains to be observed at fewer scan outputs. As a result unknowns (Xs) in the test response interfere with the good values that could be observed. Prior to this paper, Xs in the test response were treated as bad for compression and solutions either removed, bypassed, or blocked the Xs from interfering with the other res... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Evaluation of Entropy Driven Compression Bounds on Industrial Designs

    Publication Year: 2008, Page(s):13 - 18
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (206 KB) | HTML iconHTML

    The use of scan based compression techniques is becoming mandatory on current designs. While high compression is desired to hold the test costs within limits, it is important to understand the bounds set by the entropy of the care bits required by different compression techniques, to enable the selection of the right set of design and test parameters. This paper highlights the available solution s... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Untestable Fault Identification in Sequential Circuits Using Model-Checking

    Publication Year: 2008, Page(s):21 - 26
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (293 KB) | HTML iconHTML

    Similar to test pattern generation, the problem of identifying untestable faults in sequential synchronous circuits remains unsolved. The previously published works in untestability identification operate at the logic-level and, thus, they do not scale with the increasing complexity of modern designs. Current paper proposes applying model-checking for detecting untestable stuck-at faults at the re... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint

    Publication Year: 2008, Page(s):27 - 34
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB) | HTML iconHTML

    Since scan testing is not based on the function of the circuit, but rather its structure, scan testing is considered to be a form of over testing or under testing. It is important to test VLSIs using the given function. Since the functional specifications are described explicitly in the FSMs, high test quality is expected by performing logical fault testing and timing fault testing. This paper pro... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • LIFTING: A Flexible Open-Source Fault Simulator

    Publication Year: 2008, Page(s):35 - 40
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (398 KB) | HTML iconHTML

    This paper presents LIFTING (LIRMM fault simulator), an open-source simulator able to perform both logic and fault simulations for single/multiple stuck-at faults and single event upset (SEU) on digital circuits described in Verilog. Compared to existing tools, LIFTING provides several features for the analysis of the fault simulation results, meaningful for research purposes. Moreover, as an open... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Digitally-Assisted Analog/RF Testing for Mixed-Signal SoCs

    Publication Year: 2008, Page(s):43 - 48
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (430 KB) | HTML iconHTML

    We propose a testing methodology for analog and radio-frequency (RF) circuitry that incorporates digital circuits for performance calibration and adaptation. We explore the reuse of built-in digital calibration circuitry, along with minor digital design-for-testability (DfT) modifications, to test and characterize analog/RF circuit performance. By observing the digital tuning signals captured in t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low-Cost One-Port Approach for Testing Integrated RF Substrates

    Publication Year: 2008, Page(s):49 - 54
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1080 KB) | HTML iconHTML

    Low-cost testing of integrated RF substrates is necessary to reduce their production cost. In this paper a new low-cost test approach is proposed for testing an integrated RF substrate with embedded RF passive filters. As compared to a conventional test method the proposed test method reduces the test-setup cost by around 40%. The proposed method enables testing of embedded RF filters by one-port ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient Low-Cost Testing of Wireless OFDM Polar Transceiver Systems

    Publication Year: 2008, Page(s):55 - 60
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (506 KB) | HTML iconHTML

    Polar radio architectures are attractive due to the ability to implement them using largely digital architectures. However, testing for specs such as EVM incurs significant test time due to the large numbers of symbols that need to be transmitted. In our approach, EVM is modeled as a function of the system static non-idealities (IQ mismatch, gain, IIP3 parameters) and dynamic non-idealities (VCO p... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization

    Publication Year: 2008, Page(s):63 - 68
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB) | HTML iconHTML

    An interconnect-driven layout-aware multiple scan tree synthesis methodology is proposed in this paper. Multiple scan trees greatly reduce test data volume and test application time. However, previous researches on scan tree synthesis rarely considered routing length issues, and hence create scan trees with long routing paths. The proposed algorithm effectively considers both test compression rate... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sequential Circuit BIST Synthesis Using Spectrum and Noise from ATPG Patterns

    Publication Year: 2008, Page(s):69 - 74
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (219 KB) | HTML iconHTML

    ATPG patterns of a digital sequential circuit contain temporally and spatially ordered bits as well as random (or donpsilat care) bits. We synthesize BIST hardware that mimics these characteristics by controlled mixing of spectral components and noise. A Hadamard digital wave generator circuit produces all required spectral sequences and a weighted pseudorandom bit generator provides random bits. ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself

    Publication Year: 2008, Page(s):75 - 80
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (394 KB) | HTML iconHTML

    A new built-in-self-test scheme, referred to as Test Vectors Applied by Circuit-under-Test (TVAC), is proposed in this paper. As the point of view of the paper, Circuit-under-Test (CUT) is no longer only regarded as a test object, but also a kind of available resources. By feedback connecting some of the CUTpsilas interior nodes to the input terminals, the method can generate a test set with low a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.