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Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on

Date 20-23 Oct. 2008

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Displaying Results 1 - 25 of 663
  • The future of CMOS scaling - parasitics engineering and device footprint scaling

    Page(s): 21 - 24
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    We explore options for device scaling beyond the conventional scaling path. We examine the role of the parasitic capacitance for determining the performance of future one-dimensional FETs. We also explore a possible device scaling path that focuses on aggressive scaling of the contacted gate pitch, which provides performance improvements at both the device and circuit level. View full abstract»

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  • Air spacer MOSFET technology for 20nm node and beyond

    Page(s): 53 - 56
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    Two types of air spacer technologies are proposed and TCAD simulation is used to construct 20 nm-gate transistor. One is non-SAC (Self Aligned Contact) process with air spacer. It is compared with nitride-spacer and oxide-spacer transistors representing the two extremes of conventional spacer technologies. With 10 nm air spacers, the CMOS inverter delay is reduced by 45% and 30% compared to the nitride-spacer and oxide-spacer technologies respectively. Furthermore, the switching energy (power consumption) is reduced by 46% and 33% respectively. The other is SAC process with air spacer. 3D mixed mode simulation shows that the 35% area benefit can be retained while improving the speed and switching energy by 75% to be 10% better than a non-SAC device. View full abstract»

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  • Scaling study of nanowire and multi-gate MOSFETs

    Page(s): 57 - 60
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    In this paper, comprehensive comparisons of nanowire and multi-gate nMOSFETs in scaling capability using three-dimensional numerical simulations are presented. Their short channel effects and device performances are also investigated. The nanowire device requires less device dimension constraint on body diameter due to perfect surrounding gate-to-gate capacitive coupling and hence it is promising at sub-45 nm node. View full abstract»

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  • Prediction of channel thermal noise in twin silicon nanowire MOSFET (TSNWFET)

    Page(s): 61 - 63
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    In this work, channel thermal noise in the twin silicon nanowire MOSFET (TSNWFET) is predicted using analytic thermal noise model taking into account short channel effects. TSNWFET used in this work has 40 nm gate length, 5 nm radius of silicon wire, and the 3.5 nm of gate oxide. Predicted thermal noise is compared with that of the planar MOSFET using various processes. View full abstract»

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  • Thermal stability of a high performance PTGVMOS with native-tie

    Page(s): 64 - 67
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    We demonstrate thermal stability of PTGVMOS (Pseudo Tri-Gate Vertical MOSFET) with native-tie on bulk Si wafer. For comparison three types of structure are designed. According to 2D simulation, our proposed structure show excellent thermal stability, such as the lattice temperature in the drain-on-top configuration and drain-on-bottom configuration were improved 50% and 66.6% respectively. The fabricated devices have excellent on/off current ratio (61900,000 times at gate length 40 nm) in the drain-on-bottom configuration. In addition, the devices overcome short-channel effects and self heating effects significantly. View full abstract»

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  • Novel vertical sidewall MOSFETs with embedded gate

    Page(s): 68 - 71
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    In this paper we bring up a new progressive vertical structure (EGVMOS) with Embedded Gate for a MOSFET. This new structure provides not only eliminating the kink effect, but also having good gate controllability. ISE TCAD 2D simulation is carried out for evaluating its different electric characteristics. Being compared with the other vertical devices, the new device using the different implant tilts approves good results and demonstrates better device behaviors. View full abstract»

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  • Investigations on the performance limits of the IMOS transistor

    Page(s): 72 - 75
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    The Impact Ionization MOS (IMOS) transistor is a kind of promising concept as a candidate of MOS transistor due to its abrupt switching. However, some key issues will limit IMOS transistors for practical applications. In this paper, detailed physical explanations for the non-saturation of IMOS output characteristics and the unanticipated low drive current are presented. A new method to enhance the drive current of IMOS devices is reported and briefly discussed as well. View full abstract»

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  • Silicon nanowire CMOSFETs : Fabrication, characteristics, and memory application

    Page(s): 25 - 28
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    Continuous device scaling has led to the development of various transistors such as Ultra-Thin-Body SOI MOSFET, FinFET, and gate all around (GAA) MOSFETs . As the device shrinks further, the ultimate MOSFET structure would be GAA nanowire MOSFET with a fully depleted channel thoroughly controlled by the gate electrode. In this paper, fabrication processes of silicon nanowire MOSFETs on bulk Si using top-down method, their characteristics including 1D and quantum dot characteristics will be reported. Also applicable examples to memory devices such as SRAM and NAND Flash will be demonstrated. View full abstract»

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  • Low dissipation nanoscale transistor physics and operations

    Page(s): 29 - 32
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    Power dissipation has recently overtaken performance as the most important challenge in scaling nanoscale transistors. In this paper, we have proposed and preliminarily analyzed novel device concepts to reduce both the off-state leakage dissipation as well as the dynamic power consumption. The off-state leakage can be selectively suppressed using a wide bandgap drain heterojunction architecture. On the other hand, the dynamic power can be reduced using an asymmetric gate biasing scheme. We have also discussed the enabling device physics and operating principles. View full abstract»

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  • Status and trends in nanoscale Si-based devices and materials

    Page(s): 33 - 36
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    An overview of the science and technological aspects of Si-based nanodevices relevant to n+4 technology node and beyond is presented in this paper. Nanoscale CMOS and beyond-CMOS devices, based on innovative concepts, technologies and device architectures, are addressed. View full abstract»

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  • Road-blocks to Tera-level nanoelectronics

    Page(s): 37 - 40
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    The national program for Tera-level Nanodevices (TND) serves as a frontier research resource to a broad range of nanoscale electronics areas. Outstanding nanoscale devices have been achieved and are being further developed using core technologies such as fast nanoscale molecular assembly, damage-free nano-etch process with a neutral beam and nano-rod and particle formation technology. Sub-30 nm scale nonvolatile memory arrays have been demonstrated by changing structures and materials. Using high quality heterojunction epitaxial growth technology, ultra high speed HEMT devices have been demonstrated with cut-off frequencies of approximately 610 GHz corresponding to gate length of 15 nm. Additionally, single electron transistor logic circuits have been extended to multi-valued static random access memory applications. View full abstract»

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  • CMOS gate height scaling

    Page(s): 41 - 42
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    The work addresses benefits and performance impacts resulted from CMOS gate height reduction. The experiment shows that capacitance arising between the CMOS source/drain contact and the gate electrode decreases about linearly as the gate height scales down. The result also shows that stress liner techniques continue providing strong performance enhancement for CMOS as the gate height scales from 100 nm to 50 nm. For ring oscillators built with 45 nm node CMOS technology, the capacitance benefit associated with gate height reduction from 100 nm to 80 nm improves the circuit speed by ~3%. View full abstract»

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  • Extraction of voltage transfer characteristic of inverter based on TSNWFETs

    Page(s): 43 - 45
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2976 KB) |  | HTML iconHTML  

    In this paper, voltage transfer characteristic (VTC) of inverter based on Twin Silicon Nanowire MOSFETs (TSNWFETs) is extracted. TSNWFETs with 40 nm gate length and 10 nm nanowire diameter are used to construct inverter. Gain, switching threshold voltage, noise margin and transition width are extracted from VTC to show the performance of inverter based on TSNWFETs. In addition, these performance parameters are extracted by varying the supply voltage. View full abstract»

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  • An experimental study on carrier transport in silicon nanowire transistors: How close to the ballistic limit?

    Page(s): 46 - 49
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    In this paper, experimental studies on the carrier transport in silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is proposed, which takes into account the impact of quantum contact resistance. The highest ballistic efficiency is observed in sub-40 nm n-channel SNWTs due to their quasi-1D carrier transport. The apparent mobility is also extracted in comparison with the ballistic limit, which indicates that the gate-all-around SNWT can really be considered as a promising device architecture in close proximity to the ballistic transport. View full abstract»

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  • Investigation of mobility in twin silicon nanowire MOSFETs (TSNWFETs)

    Page(s): 50 - 52
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    The transport characteristics of cylindrical gate-all-around twin silicon nanowire field-effect transistors with radius of 5 nm have been investigated. Mobility was estimated by extracting of source/drain resistance. View full abstract»

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  • Novel MOSFET structures for RF applications

    Page(s): 76 - 79
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1979 KB) |  | HTML iconHTML  

    Rising demand for computing, mobile and telecommunication applications has fueled increasing efforts to integrate analog and digital functions on a single chip to create System-on-Chip (SOC) type applications. To improve RF performance of devices alternate structures must be explored to overcome problems such as degrading ROUT and gain, parasitics, noise and linearity. Towards this end, novel asymmetric Tunneling Source SOI-MOSFETs are proposed in this paper. The main feature of these devices is the concept of gate controlled carrier injection through tunneling at the source junction. The tunneling source MOSFETs can be fabricated using conventional CMOS processes. Compared to conventional SOI MOSFETs, these novel devices show excellent short channel immunity which improves scalability into sub-50 nm regime and make them an attractive candidate for analog operations. View full abstract»

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  • The impact of substrate bias on RTS and flicker noise in MOSFETs operating under switched gate bias

    Page(s): 80 - 83
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    The impact of substrate bias on random telegraph signal (RTS) and flicker noise in MOSFETs operating under switched gate bias is investigated by accurate experiments. Our results show that by applying a forward substrate bias to a MOSFET periodically switched between the nominal bias point and the OFF-state, the flicker noise is significantly suppressed. In particular, forward back bias is effective if applied during the OFF-state. Additional analysis of the RTS noise due to individual traps in small-area devices, clarify that the application of forward substrate bias to switched MOSFETs causes a large reduction of the mean emission time and increases the mean capture time, leading to a suppression of the low-frequency noise associated to the trapping de-trapping processes. View full abstract»

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  • Strain influence on analog performance of single-gate and FinFET SOI nMOSFETs

    Page(s): 84 - 87
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    This work studies the analog performance of uniaxially and biaxially strained single-gate fully depleted SOI nMOSFETs and standard and strained Si (sSOI) n-type triple-gate FinFETs with high-¿ dielectrics and TiN gate material. The analysis is performed focusing on some important analog figures of merit such as transconductance, Early voltage, output conductance and intrinsic voltage gain. It is shown that for single-gate devices the use of any kind of strain promotes the improvement of most analog parameters, resulting in a better or at least not worsen gain than for its unstrained counterpart. However for FinFETs devices, it is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas an increase of the channel length degrades the Early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. Only for wider and long FinFETs the effect of strain is favorable to both gm and gD, resulting in a larger intrinsic voltage gain than in standard FinFETs. View full abstract»

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  • Noise in nano-scale MOSFETs and flash cells

    Page(s): 88 - 91
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    In this paper, we present a compact channel thermal noise model for short-channel MOSFETs which takes into account various short channel effects. Then, we compared measured data with shot-like noise level and thermal noise model in sub-40 nm CMOS devices. Also we characterized four level RTN (Random Telegraph Noise) and extracted the characteristics of two independent traps in MOSFETs and flash cells. Their vertical, lateral locations in the oxide as well as the trap energy (ET) were obtained by using accurate equations. View full abstract»

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  • CMOS-NDR transistor

    Page(s): 92 - 95
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    In this paper, a novel device - MOS-NDR transistor is proposed and fabricated which is composed of four N-channel metal-oxide-semiconductor field effect-transistor (NMOS) devices. This MOS-NDR transistor could exhibit the negative differential resistance (NDR) characteristics similar to the conventional NDR device such as compound material based RTD (resonant tunneling diode) in the current-voltage characteristics by suitably modulating the MOS parameters, at the same time it could realize good modulation effect by the third terminal and has advantages of low working voltage (peak voltage Vp=0.7 V) and high PVCR (Peak to Valley Current Ratio) (nearly 10:1). The design and fabrication of this device are completely compatible with the standard 0.35 ¿m CMOS process, thus can considerably extend the functions of the CMOS circuits into new scope. View full abstract»

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  • 32nm Node Si and Si1−xGex SOI coplanar N channel “Vertical Dual Carrier Field Effect Transistor” for small signal mixed signal and communication applications

    Page(s): 96 - 99
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    32 nm Si and Si1-xGex SOI Coplanar N Channel Vertical Dual Carrier Field Effect Transistors for mixed signal and communication applications are presented. View full abstract»

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  • The state-of-the-art mobility enhancing schemes for high-performance logic CMOS technologies

    Page(s): 100 - 104
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (9639 KB) |  | HTML iconHTML  

    In this talk, an overview of the mobility enhancing techniques for high performance/low power CMOS technologies will be introduced first. Three categories of mobility enhancing schemes with global strain, local strain, and hybrid-substrate engineering, will be discussed next. Either nMOSET or pMOSFET has their respective strategies for achieving the best device performance. However, the strain technique has indeed raised reliability issues. Different reliability issues have been observed for different strain technologies. In the past several years, we have paid much more attention on the current performance of these technologies, the device reliability study has not been sufficient in the previous studies. As a consequence, this talk will also address the importance of these mobility enhancing schemes and their impact on the device reliability for advanced CMOS technologies which utilize strain schemes for current enhancement. View full abstract»

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  • Process characterization for strained Si on SOI CMOS devices

    Page(s): 138 - 141
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    Although the strained-Si channel engineering seems to be rather compatible with the existing mainstream CMOS process, the use of strained Si on SOI virtual substrates introduces new process and integration issues that need to be addressed for successful manufacturability and reliability. Even for ideal strained Si on SOI substrates, the impacts of various CMOS process steps, e.g., patterning, oxidation, implantation and annealing, on strain relaxation, defect formation and Ge interdiffusion need to be well understood and controlled before feasible process integration can be achieved. In this work, we investigate the influences of pad oxidation, gate oxidation and dopant-activation annealling on strained Si on SOI heterostructures by using UV micro-Raman spectroscopy in combination with other characterization techniques, such as Auger electron spectroscopy (AES), atomic force microscopy (AFM), high resolution x-ray diffraction (HRXRD), secondary ion mass spectrometry (SIMS), transmission electron microscopy (TEM). View full abstract»

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  • A theoretical study Of electrostatic properties Of 〈100〉 uniaxially strained silicon n-channel MOSFET

    Page(s): 142 - 145
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    In this paper, an accurate and efficient one dimensional self-consistent numerical solution of <100> uniaxially strained n-MOS structure is presented based on finite element method. The solution is developed using FEMLAB considering wave function penetration effect into gate oxide. Significant change occurs in the eigen energies and the electron occupancies, intrinsic carrier concentration, inversion layer penetration and gate capacitance because of <100> uniaxial tensile stress. The consequences of these changes due to strain are explained. View full abstract»

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  • Scaling of Strain-induced Mobility Enhancements in Advanced CMOS Technology

    Page(s): 105 - 108
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    Mobility enhancement by strain is a critical element in today¿s CMOS technology, and enables continued performance scaling. By modulating fundamental material properties, various strained Si techniques boost device and circuit performance independent of geometric and power supply scaling. Challenges for strained Si in aggressively scaled technology demand new ideas and materials. View full abstract»

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