Solid-State and Integrated-Circuit Technology, 2008. ICSICT 2008. 9th International Conference on
Date 20-23 Oct. 2008
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Displaying Results 1 - 25 of 663
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Scaling study of nanowire and multi-gate MOSFETs
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PDF (1941 KB)
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Road-blocks to Tera-level nanoelectronics
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PDF (3807 KB)
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CMOS gate height scaling
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PDF (2308 KB)
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An experimental study on carrier transport in silicon nanowire transistors: How close to the ballistic limit?
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PDF (2878 KB)
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Novel MOSFET structures for RF applications
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PDF (1979 KB)
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The impact of substrate bias on RTS and flicker noise in MOSFETs operating under switched gate bias
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PDF (1078 KB)
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Noise in nano-scale MOSFETs and flash cells
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PDF (2851 KB)
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CMOS-NDR transistor
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PDF (2427 KB)
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32nm Node Si and Si1−xGex SOI coplanar N channel “Vertical Dual Carrier Field Effect Transistor” for small signal mixed signal and communication applications
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PDF (2285 KB)
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The state-of-the-art mobility enhancing schemes for high-performance logic CMOS technologies
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PDF (9639 KB)
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A theoretical study Of electrostatic properties Of 〈100〉 uniaxially strained silicon n-channel MOSFET
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PDF (1339 KB)
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