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Test Conference, 2008. ITC 2008. IEEE International

Date 28-30 Oct. 2008

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Displaying Results 1 - 25 of 183
  • [Front cover]

    Page(s): C1
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  • Proceedings International Test Conference 2008

    Page(s): i
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  • [Copyright notice]

    Page(s): ii
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  • Table of contents

    Page(s): iii - xv
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  • Welcome message

    Page(s): 1
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  • Steering Committee and Subcommittees

    Page(s): 2 - 3
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  • ITC 2007 Paper Awards

    Page(s): 4
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  • ITC 2008 Most Significant Paper Award

    Page(s): 5
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  • Technical Program Committee

    Page(s): 6 - 8
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  • International Test Conference 2008 Technical Program Committee

    Page(s): 9
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  • ITC technical paper evaluation and selection process

    Page(s): 10
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  • Call for papers 2009

    Page(s): 11
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  • Managing Test in the End-to-End, Mega Supply Chain

    Page(s): 12
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    Today's "connected" environment has created significant growth opportunities in the electronics industry. Products have never been sodiverse, ranging from phones that can play movies and give directions to the nearest Starbucks to "super routers" that can move terabits worth of data around the world instantly. It is now possible to access the internet almost anywhere, including "emerging" areas which once had little to no contact at all with the rest of the world. This growth in opportunities has spurred significant supply chain growth with significant growth in both consumers and suppliers. The challenges for today's supply chain have also grown significantly with much greater diversity in products; increasing customer requirements (lower cost, faster deliver, better quality andfastertimeto market); smaller, denser, faster and more complex technology and a supply chain that now consists of thousands of suppliers and thousands of customers all over the world. All of this with a totally "virtual", global supply chain. Mike Lydon will highlight these challenges and discuss how test, and the data produced by test can either enable or disrupt these virtual supply chains. He will talk about communication in the virtual supply chain and how test can enable real time, end-to-end adjustments over the product lifecycle. Mike will conclude by presenting his vision of the test and data managed, optimized, end-to-end, global, virtual supply chain. View full abstract»

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  • Computing at the Crossroads (And What Does it Mean to Verification and Test?)

    Page(s): 13
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    Today, we are interpreting computation as the execution of complex algorithms that are executed in sequential fashion and are bound to deliver deterministic answers. A number of factors are conspiring to fundamentally change that model. First, with scaling of technology to the nanoscale dimensions, it is quite certain that the underlying hardware platform will be all but deterministic (given effects such as variability and error susceptibility). Second, the emergence of distributed computation impacts the type of algorithms that are favored. Finally, many of the interesting problems to be tackled lay in the domain of perception and cognition, and most of these challenges tend to be statistical in nature. It is hence quite plausible that the nature of computation and the underlying hardware platforms will become statistical. These trends will have a profound effect on the way we verify and test designs. It is paramount that we start to explore what all of this means today if we want to be prepared for what tomorrow will bring. View full abstract»

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  • Having FUN with Analog Test

    Page(s): 14
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    Summary form only given. Bob Pease is a legend in the analog design community. Bob has designed analog circuits for over 48 years, including 25 linear ICs and dozens of op amps and discrete circuits. As a designer for 48 years, Bob understands the importance of test engineers, test plans and test design. He also understands the implications of not getting the test done right. Bob shares the good, the bad and the ugly test experiences he's had over the years . Bob also answers pre-submitted questions during the session, making this the first interactive, invited talk in ITC history. View full abstract»

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  • This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company

    Page(s): 15
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    As cost pressures on electronic products continually increase, the urge to trim investment in test-related circuitry, activity, and equipment increases correspondingly. Not only can this strategy backfire if taken too far, but it also ignores the opportunity for test to actually add value to products. This presentation will examine the positive role that test can play and give audience members a set of guidelines to take back to their own companies so that they can perform their own analyses. Numerous examples from a variety of different electronic industries show a wide range of possible solutions. View full abstract»

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  • TTTC: Test Technology Technical Council

    Page(s): 16 - 18
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  • 2008 Technical paper reviewers

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  • Author index

    Page(s): 1 - 3
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  • [Title page]

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  • A Study of Outlier Analysis Techniques for Delay Testing

    Page(s): 1 - 10
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    This work provides a survey study of several outlier analysis techniques and compares their effectiveness in the context of delay testing. Three different approaches are studied, an Euclidean-distance based algorithm, random forest, and one-class support vector machine (SVM), from which more advanced methods are derived and analyzed. We conclude that one-class SVM using a polynomial kernel is most effective for detecting delay defects, while keeping overkills minimized. The best models were successfully validated and a feasible approach to delay testing using one-class SVM is proposed. View full abstract»

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  • Production Multivariate Outlier Detection Using Principal Components

    Page(s): 1 - 10
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    Various aspects of using principal component and related analyses to detect outliers in multiple analog measurements made on digital CMOS circuits were investigated. The focus was on implementing practical production reliability screens with an extension to analog performance tests. Experimentally examined were outlier criteria, the reproducibility of the principal component signature, and simplifications to the characterization and test flow. It was found that the best of the 5 outlier criteria examined depended on the variability of, and the degree of correlation among, the variables. It is important to perform the analysis on a sample that covers the significant variance components. It was also determined that the principal component decomposition (the signature) of a chip design is repeatable enough to be performed in characterization prior to production for IDDQ but not for a collection of other analog measurements. View full abstract»

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  • Unraveling Variability for Process/Product Improvement

    Page(s): 1 - 9
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    Manufacturing process variability compromises design aggressiveness, yield and system-level power-performance. This paper presents strategies for unraveling variability to understand its sources so that appropriate corrective action can be applied. The strategies are applied to data representing operation of finished electronic circuits, including product test results on real product hardware. View full abstract»

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  • The Test Features of the Quad-Core AMD Opteron- Microprocessor

    Page(s): 1 - 10
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    This paper describes the design-for-test (DFT) features of the quad-core AMD-OpteronTM microprocessor. View full abstract»

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  • DFX of a 3rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor

    Page(s): 1 - 10
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    The third generation CMT (chip multithreaded) microprocessor from Sun Microsystems has 16 cores and is optimized for high throughput without compromising high single thread performance. This paper describes the unique challenges faced in DFX of this complex CMT processor and the DFX solutions deployed. Some of the notable new DFX features include a highly configurable scan architecture, a memory test network that leverages functional access paths, BIST of special memories, and a test mode for running functional tests in the presence of non-deterministic serdes interfaces. Identification of chips with partially good cores and caches is supported in manufacturing for yield and in the field for availability. View full abstract»

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