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2008 IEEE International Test Conference

Date 28-30 Oct. 2008

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Displaying Results 1 - 25 of 183
  • [Front cover]

    Publication Year: 2008, Page(s): C1
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  • Proceedings International Test Conference 2008

    Publication Year: 2008, Page(s): i
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  • [Copyright notice]

    Publication Year: 2008, Page(s): ii
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  • Table of contents

    Publication Year: 2008, Page(s):iii - xv
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  • Welcome message

    Publication Year: 2008, Page(s): 1
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  • Steering Committee and Subcommittees

    Publication Year: 2008, Page(s):2 - 3
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  • ITC 2007 Paper Awards

    Publication Year: 2008, Page(s): 4
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  • ITC 2008 Most Significant Paper Award

    Publication Year: 2008, Page(s): 5
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  • Technical Program Committee

    Publication Year: 2008, Page(s):6 - 8
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  • International Test Conference 2008 Technical Program Committee

    Publication Year: 2008, Page(s): 9
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  • ITC technical paper evaluation and selection process

    Publication Year: 2008, Page(s): 10
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  • Call for papers 2009

    Publication Year: 2008, Page(s): 11
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  • Managing Test in the End-to-End, Mega Supply Chain

    Publication Year: 2008, Page(s): 12
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (491 KB) | HTML iconHTML

    Today's "connected" environment has created significant growth opportunities in the electronics industry. Products have never been sodiverse, ranging from phones that can play movies and give directions to the nearest Starbucks to "super routers" that can move terabits worth of data around the world instantly. It is now possible to access the internet almost anywhere, including "emerging" areas wh... View full abstract»

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  • Computing at the Crossroads (And What Does it Mean to Verification and Test?)

    Publication Year: 2008, Page(s): 13
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (269 KB)

    Today, we are interpreting computation as the execution of complex algorithms that are executed in sequential fashion and are bound to deliver deterministic answers. A number of factors are conspiring to fundamentally change that model. First, with scaling of technology to the nanoscale dimensions, it is quite certain that the underlying hardware platform will be all but deterministic (given effec... View full abstract»

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  • Having FUN with Analog Test

    Publication Year: 2008, Page(s): 14
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    Summary form only given. Bob Pease is a legend in the analog design community. Bob has designed analog circuits for over 48 years, including 25 linear ICs and dozens of op amps and discrete circuits. As a designer for 48 years, Bob understands the importance of test engineers, test plans and test design. He also understands the implications of not getting the test done right. Bob shares the good, ... View full abstract»

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  • This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company

    Publication Year: 2008, Page(s): 15
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (214 KB) | HTML iconHTML

    As cost pressures on electronic products continually increase, the urge to trim investment in test-related circuitry, activity, and equipment increases correspondingly. Not only can this strategy backfire if taken too far, but it also ignores the opportunity for test to actually add value to products. This presentation will examine the positive role that test can play and give audience members a s... View full abstract»

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  • TTTC: Test Technology Technical Council

    Publication Year: 2008, Page(s):16 - 18
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  • 2008 Technical paper reviewers

    Publication Year: 2008
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  • Author index

    Publication Year: 2008, Page(s):1 - 3
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  • [Title page]

    Publication Year: 2008
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  • A Study of Outlier Analysis Techniques for Delay Testing

    Publication Year: 2008, Page(s):1 - 10
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB) | HTML iconHTML

    This work provides a survey study of several outlier analysis techniques and compares their effectiveness in the context of delay testing. Three different approaches are studied, an Euclidean-distance based algorithm, random forest, and one-class support vector machine (SVM), from which more advanced methods are derived and analyzed. We conclude that one-class SVM using a polynomial kernel is most... View full abstract»

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  • Production Multivariate Outlier Detection Using Principal Components

    Publication Year: 2008, Page(s):1 - 10
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2954 KB) | HTML iconHTML

    Various aspects of using principal component and related analyses to detect outliers in multiple analog measurements made on digital CMOS circuits were investigated. The focus was on implementing practical production reliability screens with an extension to analog performance tests. Experimentally examined were outlier criteria, the reproducibility of the principal component signature, and simplif... View full abstract»

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  • Unraveling Variability for Process/Product Improvement

    Publication Year: 2008, Page(s):1 - 9
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3312 KB) | HTML iconHTML

    Manufacturing process variability compromises design aggressiveness, yield and system-level power-performance. This paper presents strategies for unraveling variability to understand its sources so that appropriate corrective action can be applied. The strategies are applied to data representing operation of finished electronic circuits, including product test results on real product hardware. View full abstract»

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  • The Test Features of the Quad-Core AMD Opteron- Microprocessor

    Publication Year: 2008, Page(s):1 - 10
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1357 KB) | HTML iconHTML

    This paper describes the design-for-test (DFT) features of the quad-core AMD-OpteronTM microprocessor. View full abstract»

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  • DFX of a 3rd Generation, 16-core/32-thread UltraSPARC- CMT Microprocessor

    Publication Year: 2008, Page(s):1 - 10
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (497 KB) | HTML iconHTML

    The third generation CMT (chip multithreaded) microprocessor from Sun Microsystems has 16 cores and is optimized for high throughput without compromising high single thread performance. This paper describes the unique challenges faced in DFX of this complex CMT processor and the DFX solutions deployed. Some of the notable new DFX features include a highly configurable scan architecture, a memory t... View full abstract»

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