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High Level Design Validation and Test Workshop, 2008. HLDVT '08. IEEE International

Date 19-21 Nov. 2008

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Displaying Results 1 - 25 of 44
  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • [Title page]

    Page(s): i
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  • [Copyright notice]

    Page(s): ii
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  • Chairs' welcome message

    Page(s): iii
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    Freely Available from IEEE
  • Committees

    Page(s): iv
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  • Table of contents

    Page(s): v - vii
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  • IC design and verification approach at Ember

    Page(s): viii
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    Freely Available from IEEE
  • Session 1: SOC verification methodologies

    Page(s): 1 - 2
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    Freely Available from IEEE
  • Positioning test-benches and test-programs in interaction-oriented system-on-chip verification

    Page(s): 3 - 10
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (543 KB) |  | HTML iconHTML  

    In simulation-based system-on-chip (SoC) verification, in addition to the testbench (TB) - the basic facility for stimulation and observation, software native to the SoC also plays a part in interacting with the SoC. This software is referred to as the test-program (TP). However, the relationship between the TB, the TP and the SoC is not always intuitive and can cause conceptual confusion. This paper discusses this confusion and shows how to address it by positioning the TB and the TP naturally in the verification framework. View full abstract»

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  • A method for hunting bugs that occur due to system conflicts

    Page(s): 11 - 17
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (381 KB) |  | HTML iconHTML  

    A very important class of bugs that occurs in VLSI projects, and especially in System on Chip (SoC) type projects, are bugs caused by two or more processes on chip trying to access a shared resource simultaneously. These kinds of bugs are both hard to find and very likely have the potential to cause a respin if not found since it is very hard to work around them in software (SW). In this paper we present a framework to define such conflict cases and a tool for automatically generating test cases from this definition. We have implemented this framework and tool, generated test suites, and simulated them on the Design Under Verification. Our method immediately proved its effectiveness by catching an unknown problem in a project which has already established a reasonable test suite regression that is simulated periodically. View full abstract»

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  • Applications of decorator and observer design patterns in functional verification

    Page(s): 18 - 22
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (235 KB) |  | HTML iconHTML  

    This paper explores the applications of decorator and observer design patterns in testbench environments. Decorator pattern is used to avoid class extension, when new responsibilities are to be added to an object. The application is presented for dynamically adding new constraints to an object. It allows creation of a pre-defined set of constraints to be used as a constraint library; whereas coding all possible combinations of constraints can result in sub-class explosion. Similar application is presented for test sequencing, where a combination of sequences/scenarios are dynamically put together to build more complex scenarios. Application of observer pattern is presented to maintain configuration consist in a chip-level testbench, when registers are accessed at runtime. In the proposed technique, re-configuration is self-maintained. A value change in a configuration register is observed by dependent modules and corresponding updates are taken place automatically. The knowledge of dependency is built as modules are attached to an observant subject. View full abstract»

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  • Session 2: Test

    Page(s): 23 - 24
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  • Test slice difference technique for low power encoding

    Page(s): 25 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1223 KB) |  | HTML iconHTML  

    In this paper, we present a low power strategy for test data compression that is called ldquobreak-independent-table (BIT) encodingrdquo. In addition, we present a new decompression scheme for test vectors that is called ldquotest slice difference techniquerdquo to solve huge test data volume that must be stored in the tester memory. About how reducing power dissipation problem, we present an extremely efficient algorithm for scan chain reordering. Experimental results for several large ISCASpsila89 benchmark circuits show that the proposed scheme achieved higher compression ratio than previous approach, and the power consumption is also significantly reduction simultaneously. View full abstract»

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  • Session 3: Panel - software practices for verification/testbench management

    Page(s): 33 - 34
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    Freely Available from IEEE
  • Panel: Software practices for verification/testbench management

    Page(s): 35 - 37
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB) |  | HTML iconHTML  

    The ever rising complexity of current hardware designs and the huge cost penalty of delivering a faulty product have led to a growing investment in functional verification and in the development of new technologies and methodologies in this area. The traditional HDL based testbenches are not proving sufficient for verification. Verification teams are switching to languages such as C++, SystemC or HVLs (High Level Verification Languages) such as Vera, e, SystemVerilog where they can manage the complexity in a more efficient manner. They are adopting concepts such as Object and Aspect Oriented Programming to impart structure to their respective verification infrastructures. In fact building a well equipped testbench for an industrial scale design is equivalent to developing quite complex software. However, such an extensive borrowing from software arena heralds the spillover of problems associated with traditional complex software development. The issues at hand are further aggravated with hardware domain specific issues such as concurrency, timing etc. View full abstract»

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  • Session 4: Formal verification

    Page(s): 38 - 40
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  • On dynamic switching of navigation for semi-formal design validation

    Page(s): 41 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB) |  | HTML iconHTML  

    Abstraction-guided simulation is a promising semi-formal framework for design validation. Unlike previously proposed approaches that utilized potentially costly abstraction-refinement for altering the abstraction when encountering hard corner cases, in this paper, a novel and low-cost method is proposed. The search begins with an initial abstraction and dynamically switches guidance to a new, different abstract model when it becomes apparent that the current model does not provide a sufficiently detailed map of the state space to advance the search towards the target. We automatically and efficiently identify those state variables that influence the circuitpsilas transition towards the target state using binary resolution, and these variables are used to create new abstractions on-the-fly during the search. The new abstractions provide a fine-grained abstract view of local segments of the concrete state space, which the stimuli generator uses to navigate towards the hard-to-reach target state. Experimental results show that our method is scalable and highly effective in reaching hard-to-reach states. View full abstract»

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  • Multi-level Bounded Model Checking to detect bugs beyond the bound

    Page(s): 49 - 55
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (322 KB) |  | HTML iconHTML  

    Bounded Model Checking is a widely used technique both in hardware and software verification. However, it cannot be applied if the bounds (number of time frames to be analyzed) becomes large. Therefore it cannot detect bugs that can be observed only through very long sequence counter-examples. In this paper, we present a method connecting multiple BMCs by sophisticated uses of inductive approach and symbolic simulation. The proposed method can check unbounded properties by analyzing loop behaviors in the design with decision procedures. In our verification flow, a property is automatically decomposed and refined instead of designs. First, a property is decomposed not to consider the reachability from the initial states of the design. Next, if a counter-example is found, the condition to enter it is generated by symbolic simulation. Finally, the reachability from the initial states to the states where the condition becomes true is checked inductively by another Bounded Model Checking. If they are not reachable from the initial states, then the property is refined not to enter the unreal counter-example. Key observation here is that each BMC does not need to process so many time frames as compared with pure BMC from initial states. Therefore, the proposed method can process much larger bounds. Experimental results with two examples have confirmed this advantage. View full abstract»

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  • Proving and disproving assertion rewrite rules with automated theorem provers

    Page(s): 56 - 63
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (331 KB) |  | HTML iconHTML  

    Modern assertion languages, such as PSL and SVA, include many constructs that are best handled by rewriting to a small set of base cases. Since previous rewrite attempts have shown that the rules could be quite involved, sometimes counterintuitive, and that they can make a significant difference in the complexity of interpreting assertions, workable procedures for proving the correctness of these rules must be established. In this paper, we outline the methodology for computer-assisted proofs of a set of previously published rewrite rules for PSL properties. We show how to express PSLpsilas syntax and semantics in the PVS theorem prover, and proceed to prove the correctness of a set of thirty rewrite rules. In doing so, we also demonstrate how to circumvent issues with PSL semantics regarding the never and eventually! operators. View full abstract»

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  • Janus: A novel use of Formal Verification for targeted behavioral equivalence

    Page(s): 64 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB) |  | HTML iconHTML  

    We present a novel way of using a formal verification (FV) framework to establish targeted behavioral equivalence between two similar designs. The new verification framework is generic and can be applied to a wide range of behavioral equivalence problems, such as ensuring late logic changes preserve earlier design intent and do not introduce new flaws. The new framework analyzes two similar designs that may have significant microarchitectural, implementation, or behavioral differences between them. If there is a targeted set of behaviors that are required to be preserved between these two designs, then the verification framework can be used to establish the behavioral equivalence. The new framework combines the strengths of FV and the formal equivalence verification (FEV) flows in a fully automated method to establish the behavioral equivalence. This method was used on one of the next generation Intelreg microprocessor to verify that design changes for a new microarchitecture feature did not create flaws or unintended behaviors (no-harm) in other parts of the design when that feature was disabled. Three complex design flaws (bugs) were found during the process. After the framework was developed, the verification effort took less than two weeks to complete which was dramatically less effort than if we had used traditional validation methods. View full abstract»

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  • Session 5: Invited session: On-chip instrumentation for silicon validation and debug

    Page(s): 71 - 72
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    Freely Available from IEEE
  • In-system silicon validation using a reconfigurable platform

    Page(s): 73
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (56 KB)  

    Summary form only given. In-system, at-speed silicon validation of a new SoC is the most time-consuming and unpredictable phase in its development process. In this talk we first review the ClearBlueTM reconfigurable platform for silicon validation and debug and then we present results from several ICs using this technology. View full abstract»

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  • On Chip Instrument application to SoC analysis

    Page(s): 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (56 KB) |  | HTML iconHTML  

    Complex SoC, including multicore technology is increasing the need for embedded instruments in ASSP, ASIC, and FPGA. This is recognized need in industry with many competing design for debug (DfD) approaches and solutions being proposed and implemented. On Chip Instruments, a hardware based method of inserting data gathering and analysis IP into a SoC, is one of the cornerstones of DfD. View full abstract»

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  • Session 6: Functional testing and verification

    Page(s): 75 - 76
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    Freely Available from IEEE
  • Test and validation of a non-deterministic system — True Random Number Generator

    Page(s): 77 - 84
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (455 KB) |  | HTML iconHTML  

    We present a validation and test methodology for a non-deterministic system, namely a True Random Number Generator (TRNG). The TRNG testing methods at Intel have matured over time, and what we present here is the 3rd generation methodology used in our latest chipset products. In addition to well known DFT and DFV techniques, testing of a TRNG requires rigorous statistical analysis to determine its proper operation. Known published works and standards donpsilat address the TRNG testing and validation issues in high volumes or their recommendations are impractical in real manufacturing constraints. We present a practical statistical methodology for TRNG testing in a high volume manufacturing environment. Its validity was proven by testing a 65-nm CMOS-based TRNG design to meet NIST standards. Our methodology can be extended to the testing of similar non-deterministic systems. View full abstract»

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