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High Level Design Validation and Test Workshop, 2008. HLDVT '08. IEEE International

Date 19-21 Nov. 2008

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Displaying Results 1 - 25 of 44
  • [Front cover]

    Publication Year: 2008, Page(s): c1
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  • [Title page]

    Publication Year: 2008, Page(s): i
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  • [Copyright notice]

    Publication Year: 2008, Page(s): ii
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  • Chairs' welcome message

    Publication Year: 2008, Page(s): iii
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  • Committees

    Publication Year: 2008, Page(s): iv
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  • Table of contents

    Publication Year: 2008, Page(s):v - vii
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  • IC design and verification approach at Ember

    Publication Year: 2008, Page(s): viii
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  • Session 1: SOC verification methodologies

    Publication Year: 2008, Page(s):1 - 2
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  • Positioning test-benches and test-programs in interaction-oriented system-on-chip verification

    Publication Year: 2008, Page(s):3 - 10
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (543 KB) | HTML iconHTML

    In simulation-based system-on-chip (SoC) verification, in addition to the testbench (TB) - the basic facility for stimulation and observation, software native to the SoC also plays a part in interacting with the SoC. This software is referred to as the test-program (TP). However, the relationship between the TB, the TP and the SoC is not always intuitive and can cause conceptual confusion. This pa... View full abstract»

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  • A method for hunting bugs that occur due to system conflicts

    Publication Year: 2008, Page(s):11 - 17
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (381 KB) | HTML iconHTML

    A very important class of bugs that occurs in VLSI projects, and especially in System on Chip (SoC) type projects, are bugs caused by two or more processes on chip trying to access a shared resource simultaneously. These kinds of bugs are both hard to find and very likely have the potential to cause a respin if not found since it is very hard to work around them in software (SW). In this paper we ... View full abstract»

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  • Applications of decorator and observer design patterns in functional verification

    Publication Year: 2008, Page(s):18 - 22
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (235 KB) | HTML iconHTML

    This paper explores the applications of decorator and observer design patterns in testbench environments. Decorator pattern is used to avoid class extension, when new responsibilities are to be added to an object. The application is presented for dynamically adding new constraints to an object. It allows creation of a pre-defined set of constraints to be used as a constraint library; whereas codin... View full abstract»

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  • Session 2: Test

    Publication Year: 2008, Page(s):23 - 24
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  • Test slice difference technique for low power encoding

    Publication Year: 2008, Page(s):25 - 32
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1223 KB) | HTML iconHTML

    In this paper, we present a low power strategy for test data compression that is called ldquobreak-independent-table (BIT) encodingrdquo. In addition, we present a new decompression scheme for test vectors that is called ldquotest slice difference techniquerdquo to solve huge test data volume that must be stored in the tester memory. About how reducing power dissipation problem, we present an extr... View full abstract»

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  • Session 3: Panel - software practices for verification/testbench management

    Publication Year: 2008, Page(s):33 - 34
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  • Panel: Software practices for verification/testbench management

    Publication Year: 2008, Page(s):35 - 37
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB) | HTML iconHTML

    The ever rising complexity of current hardware designs and the huge cost penalty of delivering a faulty product have led to a growing investment in functional verification and in the development of new technologies and methodologies in this area. The traditional HDL based testbenches are not proving sufficient for verification. Verification teams are switching to languages such as C++, SystemC or ... View full abstract»

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  • Session 4: Formal verification

    Publication Year: 2008, Page(s):38 - 40
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  • On dynamic switching of navigation for semi-formal design validation

    Publication Year: 2008, Page(s):41 - 48
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    Abstraction-guided simulation is a promising semi-formal framework for design validation. Unlike previously proposed approaches that utilized potentially costly abstraction-refinement for altering the abstraction when encountering hard corner cases, in this paper, a novel and low-cost method is proposed. The search begins with an initial abstraction and dynamically switches guidance to a new, diff... View full abstract»

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  • Multi-level Bounded Model Checking to detect bugs beyond the bound

    Publication Year: 2008, Page(s):49 - 55
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (322 KB) | HTML iconHTML

    Bounded Model Checking is a widely used technique both in hardware and software verification. However, it cannot be applied if the bounds (number of time frames to be analyzed) becomes large. Therefore it cannot detect bugs that can be observed only through very long sequence counter-examples. In this paper, we present a method connecting multiple BMCs by sophisticated uses of inductive approach a... View full abstract»

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  • Proving and disproving assertion rewrite rules with automated theorem provers

    Publication Year: 2008, Page(s):56 - 63
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (331 KB) | HTML iconHTML

    Modern assertion languages, such as PSL and SVA, include many constructs that are best handled by rewriting to a small set of base cases. Since previous rewrite attempts have shown that the rules could be quite involved, sometimes counterintuitive, and that they can make a significant difference in the complexity of interpreting assertions, workable procedures for proving the correctness of these ... View full abstract»

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  • Janus: A novel use of Formal Verification for targeted behavioral equivalence

    Publication Year: 2008, Page(s):64 - 70
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (245 KB) | HTML iconHTML

    We present a novel way of using a formal verification (FV) framework to establish targeted behavioral equivalence between two similar designs. The new verification framework is generic and can be applied to a wide range of behavioral equivalence problems, such as ensuring late logic changes preserve earlier design intent and do not introduce new flaws. The new framework analyzes two similar design... View full abstract»

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  • Session 5: Invited session: On-chip instrumentation for silicon validation and debug

    Publication Year: 2008, Page(s):71 - 72
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  • In-system silicon validation using a reconfigurable platform

    Publication Year: 2008, Page(s): 73
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB) | HTML iconHTML

    Summary form only given. In-system, at-speed silicon validation of a new SoC is the most time-consuming and unpredictable phase in its development process. In this talk we first review the ClearBlueTM reconfigurable platform for silicon validation and debug and then we present results from several ICs using this technology. View full abstract»

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  • On Chip Instrument application to SoC analysis

    Publication Year: 2008, Page(s): 74
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB) | HTML iconHTML

    Complex SoC, including multicore technology is increasing the need for embedded instruments in ASSP, ASIC, and FPGA. This is recognized need in industry with many competing design for debug (DfD) approaches and solutions being proposed and implemented. On Chip Instruments, a hardware based method of inserting data gathering and analysis IP into a SoC, is one of the cornerstones of DfD. View full abstract»

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  • Session 6: Functional testing and verification

    Publication Year: 2008, Page(s):75 - 76
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  • Test and validation of a non-deterministic system — True Random Number Generator

    Publication Year: 2008, Page(s):77 - 84
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (455 KB) | HTML iconHTML

    We present a validation and test methodology for a non-deterministic system, namely a True Random Number Generator (TRNG). The TRNG testing methods at Intel have matured over time, and what we present here is the 3rd generation methodology used in our latest chipset products. In addition to well known DFT and DFV techniques, testing of a TRNG requires rigorous statistical analysis to determine its... View full abstract»

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