2008 IEEE/ACM International Conference on Computer-Aided Design

10-13 Nov. 2008

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  • Introduction

    Publication Year: 2008, Page(s):i - ii
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  • Conference comittees

    Publication Year: 2008, Page(s):iii - vii
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  • Foreword

    Publication Year: 2008, Page(s): viii
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  • ICCAD 2008 - Awards

    Publication Year: 2008, Page(s): ix
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  • CAD for displays!

    Publication Year: 2008, Page(s): x
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  • What can brain researchers learn from computer engineers and vice versa?

    Publication Year: 2008, Page(s): x
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  • Reliable system design: Models, metrics and design techniques

    Publication Year: 2008, Page(s): xi
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    Design of reliable systems meeting stringent quality, reliability, and availability requirements is becoming increasingly difficult in advanced technologies. The current design paradigm, which assumes that no gate or interconnect will ever operate incorrectly within the lifetime of a product, must change to cope with this situation. Future systems must be designed with built-in mechanisms for fail... View full abstract»

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  • Architecting parallel programs

    Publication Year: 2008, Page(s): xi
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    The current shift from sequential to multicore and manycore processors presents serious challenges to software developers. A significant part of the industrial and research communities believes that either a) they can squeak by or b) the right compiler, parallel language etc will save them. Such ad hoc responses are likely to prove neither correct nor sustainable. To systematically find and exploi... View full abstract»

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  • Embedded software verification: Challenges and solutions

    Publication Year: 2008, Page(s): xii
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    Embedded software are becoming more and more pervasive in our lives, and many application domains have very high reliability requirements. Ensuring high software quality while still maintaining software productivity is a challenging task. In order to address this challenge, more formal analysis and automated verification techniques are needed in addition to standard software testing. View full abstract»

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  • Nanolithography and CAD challenges for 32nm/22nm and beyond

    Publication Year: 2008, Page(s): xii
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (128 KB) | HTML iconHTML

    The semiconductor industry is stuck at 193nm lithography as the main workhorse for manufacturing integrated circuits of 45nm and most likely 32nm nodes. On one hand, many novel approaches are being developed to extend the 193nm lithography, including immersion, double patterning, and exotic resolution enhancement techniques. On the other hand, next generation lithography, in particular, extreme ul... View full abstract»

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  • Challenges at 45nm and beyond

    Publication Year: 2008, Page(s): xiii
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  • Mixed-signal simulation challenges and solutions

    Publication Year: 2008, Page(s): xiii
    Cited by:  Papers (2)
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  • More Moore: Foolish, feasible, or fundamentally different?

    Publication Year: 2008, Page(s): xiii
    Cited by:  Papers (1)
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  • Table of contents

    Publication Year: 2008, Page(s):xiv - xxv
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  • Author index

    Publication Year: 2008, Page(s):xxvi - xxxiv
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  • [Copyright notice]

    Publication Year: 2008, Page(s): xxxv
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  • Network flow-based power optimization under timing constraints in MSV-driven floorplanning

    Publication Year: 2008, Page(s):1 - 8
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (238 KB) | HTML iconHTML

    Power consumption has become a crucial problem in modern circuit design. Multiple Supply Voltage (MSV) design is introduced to provide higher flexibility in controlling the power and performance trade-off. One important requirement of MSV design is that timing constraints of the circuit must be satisfied after voltage assignment of the cells. In this paper, we will show that the voltage assignment... View full abstract»

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  • Linear constraint graph for floorplan optimization with soft blocks

    Publication Year: 2008, Page(s):9 - 15
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (309 KB) | HTML iconHTML

    In this paper, we propose the linear constraint graph (LCG) as an efficient general floorplan representation. For n blocks, an LCG has at most 2n+3 vertices and at most 6n+2 edges. Operations with direct geometric meanings are developed to perturb the LCGs. We apply the LCGs to the floorplan optimization with soft blocks to leverage its advantage in terms of the sizes of the graphs, which will imp... View full abstract»

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  • A novel fixed-outline floorplanner with zero deadspace for hierarchical design

    Publication Year: 2008, Page(s):16 - 23
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (617 KB) | HTML iconHTML

    Fixed-outline floorplanning, which enables hierarchical design, is considered more and more important nowadays. In this paper, a novel SA-based Fixed-outline Floorplanner with the Optimal Area utilization named SAFFOA is introduced to improve the total wirelength. The basic idea is to build and solve a group of four quadratic equations in four variables iteratively, which can handle the fixed-outl... View full abstract»

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  • Synthesis from multi-cycle atomic actions as a solution to the timing closure problem

    Publication Year: 2008, Page(s):24 - 31
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (551 KB) | HTML iconHTML

    One solution to the timing closure problem is to perform infrequent operations in more than one cycle. Despite simplicity of the solution statement, it is not easily considered because it requires changes in RTL, which, in turn, exacerbates the verification problem. We offer a timing closure solution guaranteed to preserve functional correctness of designs expressed using atomic actions or rules. ... View full abstract»

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  • To SAT or not to SAT: Ashenhurst decomposition in a large scale

    Publication Year: 2008, Page(s):32 - 37
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (298 KB) | HTML iconHTML

    Functional decomposition is a fundamental operation in logic synthesis. Prior BDD-based approaches to functional decomposition suffer from the memory explosion problem and do not scale well to large Boolean functions. Variable partitioning has to be specified a priori and often restricted to a few bound-set variables. Moreover, non-disjoint decomposition requires substantial sophistication. This p... View full abstract»

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  • Boolean factoring and decomposition of logic networks

    Publication Year: 2008, Page(s):38 - 44
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (363 KB) | HTML iconHTML

    This paper presents new methods for restructuring logic networks based on fast Boolean techniques. The basis for these are 1) a cut-based view of a logic network, 2) exploiting the uniqueness and speed of disjoint-support decompositions, 3) a new heuristic for speeding these up, 4) extending these to general decompositions, and 5) limiting local transformations to functions with 16 or less inputs ... View full abstract»

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  • On the numbers of variables to represent sparse logic functions

    Publication Year: 2008, Page(s):45 - 51
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (314 KB) | HTML iconHTML

    In an incompletely specified function f, donpsilat care values can be chosen to minimize the number of variables to represent f. It is shown that, in incompletely specified functions with k 0psilas and k 1psilas, the probability that f can be represented with only p = 2[log2(k + 1)] variables is greater than e-1 = 0.36788. In the case of multiple-output functions, where only ... View full abstract»

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  • Effective IR-drop reduction in at-speed scan testing using distribution-controlling X-Identification

    Publication Year: 2008, Page(s):52 - 58
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (843 KB) | HTML iconHTML

    Test data modification based on test relaxation and X-filling is the preferable approach for reducing excessive IR-drop in at-speed scan testing to avoid test-induced yield loss. However, none of the existing test relaxation methods can control the distribution of identified donpsilat care bits (X-bits), thus adversely affecting the effectiveness of IR-drop reduction. In this paper, we propose a n... View full abstract»

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  • Temperature-aware test scheduling for multiprocessor systems-on-chip

    Publication Year: 2008, Page(s):59 - 66
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (200 KB) | HTML iconHTML

    Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high integrated circuit (IC) temperatures. This has the potential to damage ICs and cause good ICs to be discarded due to temperature-induced timing faults. We first study the power impact of scan chain testing for the ISCAS89 benchm... View full abstract»

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