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Solid-State Device Research Conference, 2008. ESSDERC 2008. 38th European

Date 15-19 Sept. 2008

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Displaying Results 1 - 25 of 92
  • ESSDERC 2008 Proceedings of the 38th European solid-state device research conference

    Page(s): i
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    Freely Available from IEEE
  • [Copyright notice]

    Page(s): ii
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    Freely Available from IEEE
  • Proceedings contents

    Page(s): iii
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    Freely Available from IEEE
  • Foreword

    Page(s): iv
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    Freely Available from IEEE
  • Organising Committee

    Page(s): v
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    Freely Available from IEEE
  • Steering committee

    Page(s): v
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    Freely Available from IEEE
  • ESSDERC technical programme Committee

    Page(s): v - vi
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    Freely Available from IEEE
  • ESSDERC plenary talks

    Page(s): vi
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (38 KB)  

    Provides an abstract for each of the plenary presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Sponsors

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    Freely Available from IEEE
  • ESSDERC table of contents

    Page(s): ix - xvii
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    Freely Available from IEEE
  • Venue

    Page(s): xviii
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    Freely Available from IEEE
  • Emerging device nanotechnology for future high-speed and energy-efficient VLSI: Challenges and opportunities

    Page(s): 1 - 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB) |  | HTML iconHTML  

    Emerging device nanotechnologies as well as their integration on large silicon wafers present both challenges and opportunities for future high-speed and energy-efficient digital VLSI applications. View full abstract»

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  • Micropower energy scavenging

    Page(s): 4 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (695 KB) |  | HTML iconHTML  

    More than a decade of research in the field of thermal, motion, and vibrational energy scavenging has yielded increasing power output and smaller embodiments. Power management circuits for rectification and DC-DC conversion are becoming able to efficiently convert the power from these energy scavengers. This paper summarizes recent energy scavenging results and their power management circuits. View full abstract»

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  • Solving issues of integrated circuits by 3D-stacking Meeting with the era of power, integrity attackers and NRE explosion and a bit of future

    Page(s): 10 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1505 KB) |  | HTML iconHTML  

    In the foreseeable future, VLSI design will meet a couple of explosions: explosion of power, explosion of integrity attackers including power integrity and signal integrity and explosion of NRE (non-recurring engineering cost). A remedy for power explosion and explosion of integrity attackers lies in ldquovoltage engineeringrdquo. A remedy for the NRE explosion is to reduce the number of developments and sell tens of millions of chips with a fixed design. 3D-stacked LSI approach may embody such possibility. The talk will cover example of the solutions based on 3D-stacking. Several new circuit technologies for voltage engineering, including distributed DC-DC converters and proximity interfaces are described to enable 3-D stacking of chips to build high-performance yet low-power electronics systems. On the other extreme of the silicon VLSIpsilas which stay as small as a centimeter square, a new domain of electronics called large-area integrated circuit as large as meters is waiting to open up a new continent of applications in the era of ubiquitous electronics. One of the implementations of the large-area electronics is based on organic transistors. The talk will provide perspectives of the organic circuit design taking E-skin, sheet-type scanner, Braille display and wireless power transmission and communication sheet as examples. View full abstract»

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  • Printed electronics for low-cost electronic systems: Technology status and application development

    Page(s): 17 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1672 KB) |  | HTML iconHTML  

    In recent years, printing has received substantial interest as a technique for realizing low cost, large area electronic systems. Printing allows the use of purely additive processing, thus lowering process complexity and material usage. Coupled with the use of low-cost substrates such as plastic, metal foils, etc., it is expected that printed electronics will enable the realization of a wide range of easily deployable electronic systems, including displays, sensors, and RFID tags. We review our work on the development of technologies and applications for printed electronics. By combining synthetically derived inorganic nanoparticles and organic materials, we have realized a range of printable electronic “inks”, and used these to demonstrate printed passive components, multilayer interconnection, diodes, transistors, memories, batteries, and various types of gas and biosensors. By exploiting the ability of printing to cheaply allow for the integration of diverse functionalities and materials onto the same substrate, therefore, it is possible to realize printed systems that exploit the advantages of printing while working around the disadvantages of the same. View full abstract»

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  • Overview and future challenges of Floating Body RAM (FBRAM) technology for 32nm technology node and beyond

    Page(s): 25 - 29
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (806 KB) |  | HTML iconHTML  

    Floating body cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128 Mb floating body RAM (FBRAM) with FBC has been designed and successfully developed. The memory cell design and the experimental results, including single cell (1Cell/Bit) operation, are reviewed. Based on the experimental results, the scalability of FBC is also discussed. View full abstract»

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  • The future of high-performance CMOS: Trends and requirements

    Page(s): 30 - 37
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (350 KB) |  | HTML iconHTML  

    Intrinsic MOSFET time delay is examined as a function of scaling of high-performance CMOS technology. An analytical expression is used to calculate delay from physically meaningful transistor characteristics, which are either obtained from the literature or projected forward. The key performance parameter is the calculated virtual-source carrier velocity in the channel which is shown to be responsible for the historical decrease of transistor delay with scaling. Forward projection of transistor delay is based on an optimistic scaling scenario with realistic assumptions about device geometry, electrostatic integrity, and parasitics. It is shown that from the 32-nm CMOS generation onward the intrinsic transistor performance will not improve unless parasitic capacitances are significantly reduced. Finally, characteristics of performance scaling under localized circuit power density constraints are examined. View full abstract»

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  • High mobility Ge and III–V materials and novel device structures for high performance nanoscale MOSFETS

    Page(s): 38 - 46
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1262 KB) |  | HTML iconHTML  

    In order to continue the scaling of silicon-based CMOS and maintain the historic progress in information processing and transmission, innovative device structures and new materials have to be created. A channel material with high mobility and therefore high injection velocity can increase on current and reduce delay. Currently, strained-Si is the dominant technology for high performance MOSFETs and increasing the strain provides a viable solution to scaling. However, looking into future scaling of nanoscale MOSFETs it becomes important to look at higher mobility materials, like Ge and III-V materials together with innovative device structures and strain, which may perform better than even very highly strained Si. For both Ge and III-V devices problems of leakage need to be solved. Novel heterostructure quantum-well (QW) FETs will be needed to exploit the promised advantages of Ge and III-V based devices. View full abstract»

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  • Evaluation of intrinsic parameter fluctuations on 45, 32 and 22nm technology node LP N-MOSFETs

    Page(s): 47 - 50
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (780 KB) |  | HTML iconHTML  

    The quantitative evaluation of the impact of key sources of statistical variability (SV) are presented for LP nMOSFETs corresponding to 45 nm, 32 nm and 22 nm technology generation transistors with bulk, thin body (TB) SOI and double gate (DG) device architectures respectively. The simulation results indicate that TBSOI and DG are not only resistant to random dopant induced variability, but also are more tolerant to line edge roughness induced variability. Even two technology generations ahead from their bulk counterparts, DG MOSFETs will still have 4 times less variability than bulk devices. View full abstract»

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  • A 65nm test structure for the analysis of NBTI induced statistical variation in SRAM transistors

    Page(s): 51 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    We present the results of a test structure that allows to measure the variation of SRAM p-MOS and n-MOS transistors in a dense environment and to apply Negative Bias Temperature Instability (NBTI) stress on the p-MOS transistors. The threshold voltage (Vth) and drain current (Id) distributions of p-MOS SRAM transistors pre and post NBTI Stress are measured and analyzed. The probability density functions (PDF) of both transistor parameters Vth and Id follow a Gaussian distribution pre and post NBTI stress, but the difference in the transistor parameters of an individual device is not Gaussian distributed. The standard deviation in the difference of Vth is about 50% of the mean for the small SRAM p-MOS transistor. The impact of the additional variation induced by NBTI stress is shown for the Static Noise Margin of a 6-T SRAM cell. View full abstract»

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  • An equivalent circuit model for the recovery component of BTI

    Page(s): 55 - 58
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB) |  | HTML iconHTML  

    In this work an equivalent circuit for the recoverable component of BTI is proposed. The circuit, based on diodes and capacitors for easy incorporation into circuit simulations, is able to reproduce correctly the stress, relaxation, voltage, frequency and duty factor dependences of the BTI-recovery previously reported. In addition, the model characteristics allow the extrapolation of BTI effects to very long stress times. BTI effects in a CMOS invertor have been studied using this model. View full abstract»

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  • New floating-body effect in partially depleted SOI pMOSFET due to direct-tunneling current in the partial n+ poly gate

    Page(s): 59 - 62
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (214 KB) |  | HTML iconHTML  

    A detailed analysis of the body potential impact on the performance enhancement of BC pMOSFET when the body is not contacted, is reported in this paper. Investigations on floating-body device behavior reveal that these new floating body effect leads to pMOSFET drive capability increase with lower subthreshold slope, no Ioff degradation and no kink effect. The body potential is mainly governed by the ECB component between the partial n+ poly-gate and n type silicon substrate through the 1.6 nm thin gate oxide. Static characterizations of various layouts and geometries demonstrate that narrow pMOSFET and H gate design provide the highest Ion gain due to higher body potential. Furthermore, it has been found that the largest n+ poly gate area results in the fastest switch-on Id transients. View full abstract»

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  • High-Voltage trenched rectifiers for Smart Power technology

    Page(s): 63 - 66
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB) |  | HTML iconHTML  

    High-voltage junction and Schottky trenched power rectifiers (HV-JTPR and STPR) are fabricated and analyzed in this paper for 70 V to 100 V reverse voltage applications. Resulting from their combination, an innovative hybrid device (HTPR), with alternated Schottky/Junction fingers, is a proper solution to control the trade-off between the losses in forward and reverse modes. View full abstract»

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  • DC-arc behavior of a novel active fuse

    Page(s): 67 - 70
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1296 KB) |  | HTML iconHTML  

    In this work, new results on an active fuse which is a novel power device to prevent serious hazards in power electronics in the case of a malfunction are presented. The focus of this work is on the characterization of the ldquocutout-bridgerdquo in terms of functionality and reliability. Different cutout-bridge geometries and the dc-arc behavior during fuse release is analyzed and by utilizing an additional snubber circuit to minimize the dc-arc behavior, the release time of the fuse was reduced significantly. View full abstract»

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  • Design of rugged High Voltage high power P-channel silicon MOSFET for plasma applications

    Page(s): 71 - 74
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (386 KB) |  | HTML iconHTML  

    High voltage P-channel RF MOSFET was designed and fabricated by a proprietary self-aligned VDMOS process. When this device is used for class C application at an operating frequency of 40.68 MHz and drain bias of 125 V, the CW output power can reach 350 W, and power gain is 18 dB. Therefore, this 500 V P-channel MOSFET can be used as high side switch transistor in half bridge circuit to generate more RF power for plasma applications up to 40.68 MHz. View full abstract»

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