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Digital System Design Architectures, Methods and Tools, 2008. DSD '08. 11th EUROMICRO Conference on

Date 3-5 Sept. 2008

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Displaying Results 1 - 25 of 136
  • [Front cover]

    Publication Year: 2008, Page(s): C1
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  • [Title page i]

    Publication Year: 2008, Page(s): i
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  • [Title page iii]

    Publication Year: 2008, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2008, Page(s): iv
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  • Table of contents

    Publication Year: 2008, Page(s):v - xiv
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  • Message from the Program Chair

    Publication Year: 2008, Page(s): xv
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  • Message from the General and Organizing Chairs

    Publication Year: 2008, Page(s): xvi
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  • Conference Committees

    Publication Year: 2008, Page(s):xvii - xxi
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  • Keynote Abstract: Rich Goldman

    Publication Year: 2008, Page(s): xxii
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    Summary form only given. Global Warming is hot! Climate change is occurring all around us, and the scientific evidence is increasingly overwhelming pointing to man's hand in the phenomena. We are already seeing huge impacts of Climate Change, much faster than anybody predicted only a few short years ago. What can we do about? How can we slow and even reverse our impact on Climate Change? The key m... View full abstract»

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  • Keynote Abstract: Alessandro Cremonesi

    Publication Year: 2008, Page(s): xxiii
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    Summary form only given. In his presentation, Alessandro Cremonesi will address the major challenges that the semiconductor industry will be confronted with in the context of the global ecosystem. Convergence is a clear driver for the industry and the applications fuelling the convergence are becoming increasingly complex and the need to guarantee the coexistence of a wider range of applications o... View full abstract»

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  • Keynote Abstract: Thomas Williams

    Publication Year: 2008, Page(s): xxiv
    Cited by:  Papers (19)
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    Summary form only given. Since the invention of the transistor nearly six decades ago, new technology nodes have been added approximately every two years. This march of progress has yielded smaller transistors that run about 40% faster with each geometry scaling, fulfilling the promise and industry- defining mantra of "smaller, faster, cheaper!" Now, in the realm of 65- and 45-nanometer design and... View full abstract»

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  • Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform

    Publication Year: 2008, Page(s):3 - 9
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1068 KB) | HTML iconHTML

    Interconnect validation is an important early step toward global SoC (system-on-chip) validation. Fast performances evaluation and design space exploration for NoCs (networks-on-chip) are therefore becoming critical issues. A significant speed up of the global validation process for NoC-centric SoCs could be achieved by prototyping such systems on reconfigurable devices (FPGA). However, as SoC com... View full abstract»

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  • Network Interface Sharing Techniques for Area Optimized NoC Architectures

    Publication Year: 2008, Page(s):10 - 17
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (266 KB) | HTML iconHTML

    Although preliminary analysis frameworks point out the performance speed-ups achievable by on-chip networks with respect to state-of-the-art interconnects, the area concern remains one of the most daunting challenges to make this interconnect technology mainstream. A common approach to relieve the problem consists of sharing most of network interface resources among a number of processor cores. Ho... View full abstract»

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  • Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links

    Publication Year: 2008, Page(s):18 - 25
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (397 KB) | HTML iconHTML

    In this paper we propose a series of efficient routing strategies to effectively utilize NoC systems with partially faulty links. These strategies try to use partially faulty links when the load is high and distribute traffic uniformly on links. Evaluation of our strategies for 8times8 mesh with 7% partially faulty links shows that, using our best strategy, it is possible to achieve an average red... View full abstract»

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  • CART: Communication-Aware Routing Technique for Application-Specific NoCs

    Publication Year: 2008, Page(s):26 - 31
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (207 KB) | HTML iconHTML

    Networks on Chip (NoCs) have been shown as an efficient solution to the complex on-chip communication problems derived from the increasing number of processor cores. One of the key issues in the design of NoCs is the reduction of both area and power dissipation. As a result, two-dimensional meshes have become the preferred topology, since it offers low and constant link delay. Unfortunately, manuf... View full abstract»

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  • LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control

    Publication Year: 2008, Page(s):32 - 35
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (426 KB) | HTML iconHTML

    This work presents a low-complexity physical link micro architecture for a mesochronous on-chip communication insensitive to clock skew. This new link architecture, called LIME, integrates a low-latency flow control scheme; this feature may ease the set up of reliable Network-on-Chip infrastructures. The proposed architecture also supports virtual channels that are multiplexed on a single physical... View full abstract»

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  • Flexible Baseband Architectures for Future Wireless Systems

    Publication Year: 2008, Page(s):39 - 46
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (279 KB) | HTML iconHTML

    The mobile communication systems today, have different radio spectrum, radio access technologies, and protocol stacks depending on the network being utilized. This gives rise to need of a flexible hardware platform that is capable of supporting all the different standards in the entire wireless communication frequency range. We present a generic baseband prototype architecture for SDR applications... View full abstract»

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  • A Lightweight Operating Environment for Next Generation Cognitive Radios

    Publication Year: 2008, Page(s):47 - 52
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (666 KB) | HTML iconHTML

    It is widely known that the SDR industry campaigns component-based radio applications, which will enable fast prototyping and deployment of new radio devices and may increase manufacturing profits. Through the JTRS program, the US Dept. of Defense proposed the SCA specification as the standard for military communications. The SDR Forum is now reviewing these specifications and trying to adapt them... View full abstract»

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  • On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip

    Publication Year: 2008, Page(s):53 - 60
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB) | HTML iconHTML

    This paper introduces a state-of-the-art design of a high speed sigma delta digital to analog converter (DAC), which can be integrated into a system-on-a-chip (SOC) for different communication transceivers. The operation speed in the digital circuit is very important for accomplishing the performance which can satisfy different communication protocol specifications. This paper therefore addresses ... View full abstract»

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  • A Reconfigurable LFSR for Tri-standard SDR Transceiver, Architecture and Complexity Analysis

    Publication Year: 2008, Page(s):61 - 67
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (736 KB) | HTML iconHTML

    In the Software Radio (SWR) Area, techniques of parameterization are an active research topic. These techniques factorize common functions or operators and in consequence lead to compact though open implementation. However, reconfigurability is often achieved at the cost of additional configuration logic and the benefit of factorization must be carefully analysed. This paper is dedicated to a Reco... View full abstract»

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  • Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems

    Publication Year: 2008, Page(s):71 - 80
    Cited by:  Papers (1)
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    In this paper we present an approach for scheduling with preemption for fault-tolerant embedded systems composed of soft and hard real-time processes. We are interested to maximize the overall utility for average, most likely to happen, scenarios and to guarantee the deadlines for the hard processes in the worst case scenarios. In many applications, the worst-case execution times of processes can ... View full abstract»

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  • Digital Systems Architectures Based on On-line Checkers

    Publication Year: 2008, Page(s):81 - 87
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (177 KB) | HTML iconHTML

    In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of communication protocols, counters, decoders, registers, comparators, etc. It is also demonstrated how a checker for more complex structures can be developed. We describe the possibilities of utilizing this approach in the desig... View full abstract»

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  • Fault Models and Injection Strategies in SystemC Specifications

    Publication Year: 2008, Page(s):88 - 95
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (565 KB) | HTML iconHTML

    This paper presents fault models and fault injection strategies designed in a simulation platform with reflection capabilities, used for simulating complex systems specified by using SystemC and by adopting a platform-based design approach. The approach allows the designer to work at different levels of abstraction and to take into account permanent and transient faults, and -- most important -- i... View full abstract»

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  • An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA

    Publication Year: 2008, Page(s):96 - 99
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    We propose a method to efficiently design a "parity generator", which is a stand-alone block producing multiple parity bits of a given circuit. The parity generator is designed by duplicating the original circuit, XOR-ing given groups of its outputs and resynthesizing the whole circuit. The resulting circuitry is mostly smaller than the original circuit. The major task to be solved is to properly ... View full abstract»

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  • Experimental SEU Impact on Digital Design Implemented in FPGAs

    Publication Year: 2008, Page(s):100 - 103
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (247 KB) | HTML iconHTML

    The main aim of our research is to investigate the influence of SEU on a digital circuit implemented in FPGA. The FPGA resources occupied by design are divided into several groups. SEU impact is investigated for each group. To make a real dependability model the real effects of injected errors and faults have to be studied. The SEU emulator deals with single-bit change in bitstream. Emulation is p... View full abstract»

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