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Thermal Inveatigation of ICs and Systems, 2008. THERMINIC 2008. 14th International Workshop on

Date 24-26 Sept. 2008

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Displaying Results 1 - 25 of 55
  • Collection of papers presented at the 14th International Workshop on THERMal INvestigation of ICs and Systems

    Page(s): I
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    Freely Available from IEEE
  • [Copyright notice]

    Page(s): II
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    Freely Available from IEEE
  • Workshop Committee and Programme Committee

    Page(s): III
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    Freely Available from IEEE
  • [Blank page]

    Page(s): IV
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    Freely Available from IEEE
  • Preface

    Page(s): V
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    Freely Available from IEEE
  • [Blank page]

    Page(s): VI
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    Freely Available from IEEE
  • Table of contents

    Page(s): VII - X
    Save to Project icon | PDF file iconPDF (329 KB)  
    Freely Available from IEEE
  • CFD for Electronics Cooling: MCAD and EDA embedded vs. stand-alone

    Page(s): 1 - 7
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (695 KB) |  | HTML iconHTML  

    Computational fluid dynamics (CFD) for electronics cooling (EC) has developed differently from general-purpose CFD, due to the nature of the market it serves. The benefits are clear - the use of EC CFD in product design has had a profound impact on both time-to-market and cost. View full abstract»

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  • Triangulation method for structure functions of multi-directional heat-flows

    Page(s): 8 - 13
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (559 KB) |  | HTML iconHTML  

    In this paper previous results proposed by the authors for localizing defects in components and packages by means of structure functions in three-dimensional heat diffusion problems have been generalized. To this aim a novel traingulation approach is presented based on the use of structure functions corresponding to dinstinct heat sources. View full abstract»

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  • Transient dual interface measurement of the Rth-JC of power packages

    Page(s): 14 - 19
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (416 KB) |  | HTML iconHTML  

    The accurate and reproducible measurement of the junction-to-case thermal resistance Rth-JC of power semiconductor devices is far from trivial. In the recent time several new approaches to measure the Rth-JC have been suggested, among them transient measurements with two different interface layers between the package and a heat-sink. The Rth-JC can be identified either in the structure functions or at the point of separation of the two Zth-curves or their derivatives. Further investigations revealed however that the latter approach is restricted to power packages with solder die attach and cannot be applied to devices with thermally low conductive glue die attach since an internal heat flow barrier falsifies the measurement result. After recapitulating the transient dual interface measurement and its evaluation using the derivatives of the Zth curves, a detailed investigation of this method by means of finite element simulations is presented herein. View full abstract»

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  • Evaluation of short pulse thermal transient measurements

    Page(s): 20 - 25
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (403 KB) |  | HTML iconHTML  

    Thermal transient recording and the time constant spectrum analysis are widely used methods in the testing and qualification of IC packages. A limitation of these methods is that recording of the complete transient response requires long time. The paper offers algorithms to evaluate short pulse and short time measurements. These methods are suitable if only the extraction of the short time constants are needed. This is the case if the transient method is used for die attach quality checking. View full abstract»

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  • New approach for thermal investigation of a III – V power transistor

    Page(s): 26 - 30
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (395 KB) |  | HTML iconHTML  

    In this paper is presented a new method for characterisation of temperature of AlGaN-GaN transistor. An ellipsometer is also explained for measure of refractive index and so propagation time constant. View full abstract»

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  • Ensuring temperature-insensitivity of dual-Vt designs through ITD-aware synthesis

    Page(s): 31 - 36
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (425 KB) |  | HTML iconHTML  

    In old CMOS technologies above 90 nm, operating a circuit in high-temperature regime was implying an increase in the total delay. This was due to the fact that both interconnects and gates were slowing down as temperature was raising. For transistors with feature size of 90 nm and below, this picture started changing. In particular, the threshold voltage to supply voltage ratio of high-Vt cells in a library is now very close to 1. Consequence of this is the appearance of the so-called Inverted Temperature Dependence (ITD) of the propagation delay of such cells. In other words, while for low-Vt gates the delay does increase with temperature, high-Vt gates show the opposite behavior; they get faster as they get warmer. This new, complicated dependence of delay vs. temperature poses new challenges to circuit designers and, in turn, to the EDA tools. Besides making timing analysis more difficult, ITD has important and unforeseeable consequence for power-aware logic synthesis. Expanding on our recent work [1], [2], this paper describes the impact that ITD may have on the design of modern, nanometer VLSI circuits. We also provide a more refined algorithm for dual-Vt synthesis which guarantees temperature-insensitive operation of the circuits, together with a significant reduction of both leakage and total power consumption. In fact, experiments performed on a set of standard benchmarks show timing compliancy at any temperature, and an average leakage reduction around 22% w.r.t. circuits synthesized with a standard, commercial flow that does not take ITD into account and thus, to ensure that no temperature-induced timing faults occur, needs to resort to overdesign (i.e., overconstraining the timing bound so as to make sure that temperature fluctuations never make the circuits violating the specified required time for all paths). View full abstract»

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  • Managing leakage power and reliability in hot chips using system floorplanning and SRAM design

    Page(s): 37 - 42
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (480 KB) |  | HTML iconHTML  

    Increased operating temperatures of chips have aggravated leakage and reliability issues, both of which are adversely affected by high temperature. Due to thermal diffusion among IP-blocks and the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a system on chip (SoC). An increase in temperature also increases the probability of errors such as read/write errors or unstable memory accesses. In a thermal unaware paradigm, SRAM designers increase (overdrive) the supply voltage (Vdd) to increase their reliability. However, increasing Vdd in turn increases the memorypsilas leakage and dynamic power dissipation and its temperature is elevated. Thus Vdd, power, temperature, and probability of errors influence each other mutually and must be considered during SRAM design. This paper addresses two issues: (i) we propose a novel system level leakage aware floorplanner which optimizes floorplans for thermal-aware leakage power along with the traditional metrics of area and wire length; and (ii) we demonstrate the effect of temperature on the probability of errors of SRAM memories which helps designers select a thermal-aware operating voltage for SRAMs. We will also discuss temperaturehArrleakage positive feedback loop. We applied our floorplanner on eight industrial SoC designs from Freescale Semiconductor Inc. and we observed up to 135% difference in the leakage power between leakage-unaware and leakage aware floorplanning. In this paper we also quantify the effect of temperature on the probability of failures in memories. We observed that by considering the effect of temperature on memories, reducing Vdd can help improve both the reliability and the power dissipation. For a predefined limit on reliability, thermal aware Vdd selection can reduce the total power dissipation by up to 2.5X. View full abstract»

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  • Assessment of die attach quality by analysis of circuit thermal response spectrum

    Page(s): 43 - 46
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (507 KB) |  | HTML iconHTML  

    This paper investigates the possibility of assessing the die attach quality by the spectral analysis of the recorded device time response. The conducted analyses of the measured and the simulated time constant spectra of the thermal response allowed the explanation of the anomalous electrical oscillations observed during the operation of a power converter. View full abstract»

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  • Material characterization and non-destructive failure analysis by transient pulse generation and IR-thermography

    Page(s): 47 - 51
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (757 KB) |  | HTML iconHTML  

    IR-thermography has become increasingly important for non-destructive testing of microelectronic devices and structures on chip, package and board-level. This paper focuses on the evaluation of best applicability for different pulse excitation modes to detect flaws and damages as well as to determine material properties. Pulse IR thermography using electrical and laser excitation was chosen as an analytic method to observe and quantify crack growths in vias under thermal cycling load. We found that cracks are detectable unambiguously and its advantage over the ohmic test. The laser excitation in contrast to the electrical excitation has a good potential for large-scale screening as the board can be stepwise thermally excited and screened in one go without having any additional measuring lines. A new concept detecting crack tips was demonstrated. View full abstract»

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  • Compact thermal networks for conjugate heat transfer by moment matching

    Page(s): 52 - 57
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (388 KB) |  | HTML iconHTML  

    The problem of constructing compact thermal models for conjugate heat transfer problems is faced. A novel notion of thermal multi-port modeling conjugate heat transfer is given and a novel moment matching method is introduced for constructing compact models of such thermal multi-ports. The resulting compact models preserve the passivity and reciprocity properties of the original thermal problem and can exhibit high levels of accuracy and compactness. View full abstract»

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  • Block-level thermal model for floorplan stage in VLSI design flow

    Page(s): 58 - 63
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (441 KB) |  | HTML iconHTML  

    Thermal issues have become a determinant factor to result in very large scale integrated (VLSI) circuits work or malfunction. For this reason, the paper proposed an efficient block-level thermal model for temperature calculation in the floorplan stage among the integrated circuit (IC) design flow. Furthermore, the model accurately profiles the temperature difference between all thermal blocks and overcomes the very long computational time issue existing in traditional tile-based thermal model. We not only prove the timing complexity by theory but also use five floorplan benchmarks to test our model. Observing the experimental results, the temperature calculation times for all benchmarks are really direct ratio of total amount of blocks. Hence our block-level thermal model really can reduce the temperature calculating time and provide useful temperature differences for rearranging the floorplan. View full abstract»

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  • Multiscale 3D thermal analysis of analog ICs: From full-chip to device level

    Page(s): 64 - 69
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (2557 KB) |  | HTML iconHTML  

    We have developed and employed an automated multi-scale modeling approach to investigate thermal issues in analog integrated circuits (ICs) and to enable ldquothermally awarerdquo design thereof. Thermal analysis from full-chip scale down to the single transistor level was made possible with this approach utilizing the finite volume three-dimensional (3D) numerical technique. We have developed new methods and tools that import GDSII layout of entire IC and generate 3D model. The tool provides a 3D temperature map that can show thermal gradients across a chip, as well as local temperature distribution (hot spots) down to single transistor level. This allows introducing temperature back into design process. Our method and tools are demonstrated on a couple of radio-frequency (RF) chips. The multiscale modeling has been verified with infrared temperature measurements. View full abstract»

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  • The minimal set of parameters for exact dynamic thermal models

    Page(s): 70 - 75
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (458 KB) |  | HTML iconHTML  

    A thermal model is presented that follows from the heat conduction equation and is exact under the conditions that the mass density, the specific heat and the thermal conductivity in the set-up do not depend on temperature and that the individual thermal contact areas of the models have uniform temperature distribution. The network models allow for the determination of both: the transient temperatures at specified thermal contacts and the associated heat flows at the contact areas. Compared to previous models, the network of the reduced compact model consists of one-port impedance links between external terminals and one reference node, which is explicitly added. When m is the number of thermal device contact areas and p the number of heat sources, the model is characterized by (m + p +1) (m + p ) / 2 one-port impedances with its associated R, C, L elements. A methodology is investigated for the determination of the network parameters, which poses in many cases a highly ill conditioned problem, which may render the results useless. Alternative methods are suggested. View full abstract»

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  • Automatic electro-thermal analysis in Mentor Graphics PCB Design System

    Page(s): 76 - 79
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (557 KB) |  | HTML iconHTML  

    Automatic electro-thermal analysis is included into mentor graphics PCB design system. The method of simultaneous iteration is used for board-level electro-thermal simulation. New software tool named TransPower is introduced to couple the electrical (Analog Designer) and thermal (BETAsoft) simulators. The design procedure is fully automated, human errors are eliminated, simulation time is significantly decreased, while accuracy and reliability are increased. View full abstract»

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  • Integrated thermal modeling of heterogeneous eCubes stacked devices

    Page(s): 80 - 84
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1713 KB) |  | HTML iconHTML  

    Vertical chip integration applied in heterogeneous systems is a design approach used to extend the device functionality and improve its performance. Apart from the design advancements, thermal budget of the device is constrained internal structure of the device. Internal module components limit the efficiency of device cooling. It is one of the most important concerns of vertical integration reliability. Development of vertically integrated devices requires cooperation of different partners and designers. This paper presents thermo-mechanical simulation needs and capabilities. The presented HDL approach is used for thermal modeling of the structure and high level, NDA-proof thermal simulations of modules of stacked, heterogeneous devices. View full abstract»

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  • logical effort model extension with temperature and voltage variations

    Page(s): 85 - 88
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (650 KB) |  | HTML iconHTML  

    The method of ldquoLogical Effort Delay Modelrdquo allows designers to quickly estimate delay time and optimize logic paths. But the previous variances of logical effort models do not mention how to handle process, voltage, and temperature (PVT) variations appropriately, which may induce a serious misestimate. According to simulation results, delay time increases 21% while temperature increasing from 0degC to 125degC, and increases 2X while supply voltage decreasing from 1 V to 0.5 V in 90nm process. Thus a simple linear extended logical effort g, 1/g=(mtt+bt)VDD+C, supporting for temperature t and supply voltage VDD variations is presented. The proposed model enables designers to estimate the logic path delay and to optimize an N-stage logic network under different temperature and supply voltage conditions. After validation, the accuracy of this new extended logical effort model can achieve about 90%. View full abstract»

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  • A novel procedure and device to allow comprehensive characterization of power leds over a wide range of temperature

    Page(s): 89 - 92
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (707 KB) |  | HTML iconHTML  

    LEDs are key elements in modern, energy efficient lighting solutions as well as impose some issues from thermal point of view, since light output and reliability both depend on LEDspsila junction temperature. A comprehensive and accurate measurement method is required and demanded by several leader LED manufacturers. Failing a proper combined thermal and radiometric/photometric characterization of LED light sources it is impossible to fulfill the reliability prescriptions for LEDs and to trust the lifetime estimation given in LED datasheets. Light output of LEDs is typically measured in integrating spheres. A key element in such a total flux measurement setup is the appropriate set of standard LEDs which are both current and temperature stabilized and are accompanied with certificate values of their own total flux traceable to primary etalons of national measurement laboratories. So far there are hardly any such standard LEDs available for the high power range. In this paper we describe the design of such a device (having 5 colors) and describe a modification of the substitution type total flux measurement method which is suitable for an automated, comprehensive measurement of LEDs over a wide range of operating conditions. View full abstract»

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  • Multi-physics analysis of a photovoltaic panel with a heat recovery system

    Page(s): 93 - 96
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (382 KB) |  | HTML iconHTML  

    This paper presents a multi-physics analysis of a hybrid solar panel equipped with a solar concentrator and a cooling interface with heat recovery capability. It is shown that the analysis allows one to predict the temperature profile along the panel as well as the I-V electrical characteristic as a function of the cooling strategy. View full abstract»

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