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VLSI Test Symposium, 1997., 15th IEEE

Date April 27 1997-May 1 1997

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Displaying Results 1 - 25 of 65
  • Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (2019 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1997, Page(s):465 - 466
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    Freely Available from IEEE
  • Obtaining high fault coverage with circular BIST via state skipping

    Publication Year: 1997, Page(s):410 - 415
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    Despite all of the advantages that circular BIST offers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic tha... View full abstract»

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  • Highly testable and compact single output comparator

    Publication Year: 1997, Page(s):210 - 215
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    In this paper a single output self-checking n-input comparator is presented. The proposed circuit, which can be used as n-variable two-rail checker or as equality checker features a compact structure, is Totally-Self-Checking or Strongly Code-Disjoint with respect to a wide set of realistic faults, and requires a limited set of input code words for fault detection (thus it can be used to implement... View full abstract»

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  • Salvaging test windows in BIST diagnostics

    Publication Year: 1997, Page(s):416 - 425
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (876 KB)

    This paper uses the STUMPS architecture to study the properties of a new diagnostic procedure. According to the old procedure the process stops at the end of each test window to compare the measured signature against its precomputed value. The old procedure also calls for the abandonment of all future test windows after the first failing one is encountered. This is due to the unavailability of exp... View full abstract»

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  • Critical hazard free test generation for asynchronous circuits

    Publication Year: 1997, Page(s):203 - 208
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    We describe a technique to generate critical hazard-free tests for self-timed control circuits built using a macro-module library, in a partial scan based DFT environment. We propose a six-valued algebra to generate these tests which are guaranteed to be critical hazard free under an unbounded delay model. This algebra has been incorporated in a D-algorithm based automatic test pattern generator View full abstract»

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  • Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS

    Publication Year: 1997, Page(s):177 - 182
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    It is important to predict noise at the early stages of a top down design. In this paper, we propose a methodology to model phase noise or jitter, a key specification for phase-locked loops, using a mixed-signal hardware description language, and to simulate the effects of catastrophic faults on the phase jitter at the behavioral level. In contrast to existing approaches which either require dedic... View full abstract»

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  • Test of RAM-based FPGA: methodology and application to the interconnect

    Publication Year: 1997, Page(s):230 - 237
    Cited by:  Papers (63)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    This paper proposes a methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices. Two different approaches with different objectives are identified: the Manufacturing Test Procedure and the User Test Procedure. The proposed method is used to generate a Manufacturing Test Procedure targeting the Interconnect Structure of RAM-based FPGA. It is demonstrate... View full abstract»

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  • Assessing SRAM test coverage for sub-micron CMOS technologies

    Publication Year: 1997, Page(s):24 - 30
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    This paper proposes a realistic memory fault probability model which predicts the probabilities of memory fault classes for a given process technology. Physical defects in the memory array are classified into five functional fault classes, which are stuck-at, stuck-open, transition, coupling, and data retention faults. Finally, the memory fault coverages of the known memory test algorithms are eva... View full abstract»

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  • Extension of inductive fault analysis to parametric faults in analog circuits with application to test generation

    Publication Year: 1997, Page(s):172 - 176
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    Parametric fault modeling methodology based on statistical process simulation is proposed. Statistical simulation based on process disturbances allows one to avoid testing for faults which are unlikely to occur. As a result, the number of tests required to verify the circuit's performance is reduced. A practical example with results measured on prototype chips is presented View full abstract»

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  • Testability of sequential circuits with multi-cycle false paths

    Publication Year: 1997, Page(s):322 - 328
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    This paper investigates the relationship between multi-cycle false paths and the testability of sequential circuits. We show that removal of multi-cycle false paths (either by circuit restructuring or by proper state encoding) improves circuit testability, though not as significantly as one would expect. We then investigate the use of partial scan. We demonstrate the inability of current structure... View full abstract»

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  • Robust sequential fault testing of iterative logic arrays

    Publication Year: 1997, Page(s):238 - 244
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    Technology advances provide today the capability of integrating large Iterative Logic Arrays (ILAs) in the same chip. Traditional combinational fault models are not sufficient to detect all failures in CMOS ILAs. Robust test generation for sequential faults in ILAs has not been considered in the literature. Two-pattern tests for sequential fault detection in ILAs can be invalidated either at the c... View full abstract»

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  • An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing

    Publication Year: 1997, Page(s):459 - 464
    Cited by:  Papers (98)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    This paper describes an experiment in which various semiconductor test methodologies (stuck-fault, functional, delay and IDDq) are applied to an ASIC device. The goal of this project is to provide the data that will enable manufacturers to optimize their application of the various tests. This project was supported through SEMATECH (Project S-121, “Semiconductor Test Method Evaluation ”... View full abstract»

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  • Experimental fault analysis of 1 Mb SRAM chips

    Publication Year: 1997, Page(s):31 - 36
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Analyzing 1,000 faulty 1 Mb SRAM chips that were randomly selected from a single manufacture, we found 251 stuck-at cell faults, 5 stuck-at bit-line faults, 1 stuck-at word-line fault, 46 neighborhood-pattern-sensitive faults, and other kinds of faults. Under the condition that Idd=4.5 I; temperature=70°C, and load capacity CL=30 pF, we detected margin faults in 460 chips... View full abstract»

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  • Built-in parametric test for controlled impedance I/Os

    Publication Year: 1997, Page(s):123 - 128
    Cited by:  Papers (1)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    A test method for functional and parametric test of I/Os has been developed. This method allows I/Os to be tested in parallel by use of a common DC supply instead of individual tester channels and pin electronics. Full DC parametrics on inputs and outputs, and full speed AC tests, can be performed on lower cost ATE. Both single-ended and differential signal I/Os are handled. Differential measureme... View full abstract»

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  • High-level synthesis for orthogonal scan

    Publication Year: 1997, Page(s):370 - 375
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    Scan paths are commonly used in digital design to improve the testability of sequential circuits since a full scan path provides complete controllability and observability for every bistable element. A traditional scan path is implemented after the circuit has been designed, with little regard to the actual circuit function. High-level synthesis can exploit knowledge of the circuit function to syn... View full abstract»

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  • Differential sensing strategy for dynamic thermal testing of ICs

    Publication Year: 1997, Page(s):434 - 439
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    A new testing alternative based on thermal wave propagation is proposed. Some failures, when activated, produce an increase in local power dissipation at various points. A thermal wave is generated by this increase and can be used as a test observable. In this paper, both the thermal wave and the heat sources that appear for a set of faults are characterised and a built-in sensing strategy based o... View full abstract»

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  • Fault coverage of a long random test sequence estimated from a short simulation

    Publication Year: 1997, Page(s):391 - 398
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (888 KB)

    Forecasting the fault coverage of a long random test sequence from the results obtained from the simulation of a short test sequence looks like an inaccessible dream. As a matter of fact, a short test sequence detects mainly easy to detect faults, while the test length required for a fault coverage close to 1 depends mainly (almost only) on the most difficult faults. A new 2-parameter model, linki... View full abstract»

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  • Testing embedded cores using partial isolation rings

    Publication Year: 1997, Page(s):10 - 16
    Cited by:  Papers (63)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    Intellectual property cores pose a significant test challenge. The core supplier may not give any information about the internal logic of the core, but simply provide a set of test vectors for the core which guarantees a particular fault coverage. If the core is embedded within a larger design, then the problem is how to apply the specified test vectors to the core and how to test the user-defined... View full abstract»

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  • Parametric and catastrophic fault coverage of analog circuits in oscillation-test methodology

    Publication Year: 1997, Page(s):166 - 171
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    This paper investigates parametric and catastrophic fault coverage of the oscillation-test strategy. A set of definitions to evaluate the efficiency of a test technique and to quantify the parametric fault coverage is therefore introduced. The oscillation-test strategy is a low-cost and practical test method which is very efficient for built-in self-testing of mixed-signal integrated circuits. Act... View full abstract»

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  • Self-exercising self testing k-order comparators

    Publication Year: 1997, Page(s):216 - 221
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    In this paper we give a systematic method to design self-exercising (SE) self testing k-order comparators. The k-order comparator is defined as a combinational circuit that compares two operands and decides if these differ in less than k bits. According to this definition the usual equality comparator is the 1st-order comparator. Also in this paper we discuss the applicability of the k-order compa... View full abstract»

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  • A DFT technique for analog-to-digital converters with digital correction

    Publication Year: 1997, Page(s):302 - 307
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    Pipeline or sub-ranging architectures enable the implementation of high-speed, low-power and high-resolution Analog-to-Digital Converters (ADCs). It is usual in these architectures to include digital correction to reduce the sensitivity to certain component nonlinearities, such as comparator offsets and settling errors. However, digital correction makes difficult the detection of defective operati... View full abstract»

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  • An on-line testable UART implemented using IFIS

    Publication Year: 1997, Page(s):344 - 349
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB)

    This paper presents the design of a complex integrated circuit realised through a novel on-line test methodology. The circuit and its exact conventional equivalent both have been realised in FPGA technology. As such it represents one of the more complex designs realised to date using on-line test approaches. The approach used IFIS (If it Fails It Stops) incorporates dual-rail coding of individual ... View full abstract»

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  • Methods to reduce test application time for accumulator-based self-test

    Publication Year: 1997, Page(s):48 - 53
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    Accumulators based on addition or subtraction can be used as test pattern generators. Some circuits, however, require long test lengths if the parameters of the accumulator are not properly adapted. This paper presents two different methods to minimize the test length without sacrificing fault coverage. The simulation-based reseeding method is suited to random pattern testable circuits and uses fo... View full abstract»

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  • An optimized BIST test pattern generator for delay testing

    Publication Year: 1997, Page(s):94 - 100
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (640 KB)

    As delay testing using external testers requires expensive equipment, built-in self-test (BIST) is an alternative technique that can significantly reduce the test cost. In this paper, a BIST test pattern generator (TPG) design for the detection of delay faults is proposed. This TPG design produces test sequences having exactly the same robust delay fault coverage as single input change (SIC) test ... View full abstract»

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