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VLSI Test Symposium, 1997., 15th IEEE

Date April 27 1997-May 1 1997

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Displaying Results 1 - 25 of 65
  • Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125)

    Publication Year: 1997
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    Freely Available from IEEE
  • Author index

    Publication Year: 1997 , Page(s): 465 - 466
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    Freely Available from IEEE
  • Diagnostic test pattern generation for sequential circuits

    Publication Year: 1997 , Page(s): 196 - 202
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (644 KB)  

    A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at primary input in the modified circuit techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits. Speed-up of the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic View full abstract»

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  • Critical hazard free test generation for asynchronous circuits

    Publication Year: 1997 , Page(s): 203 - 208
    Cited by:  Papers (2)
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    We describe a technique to generate critical hazard-free tests for self-timed control circuits built using a macro-module library, in a partial scan based DFT environment. We propose a six-valued algebra to generate these tests which are guaranteed to be critical hazard free under an unbounded delay model. This algebra has been incorporated in a D-algorithm based automatic test pattern generator View full abstract»

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  • Obtaining high fault coverage with circular BIST via state skipping

    Publication Year: 1997 , Page(s): 410 - 415
    Cited by:  Papers (4)
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    Despite all of the advantages that circular BIST offers compared to conventional BIST approaches in terms of low area overhead, simple control logic, and easy insertion, it has seen limited use because it does not reliably provide high fault coverage. This paper presents a systematic approach for achieving high fault coverage with circular BIST. The basic idea is to add a small amount of logic that causes the circular chain to skip to particular states. This “state skipping” logic can be used to break out of limit cycles, break correlations in the test patterns, and jump to states that detect random-pattern resistant faults. The state skipping logic is added in the chain interconnect and not in the functional logic, so no delay is added to system paths. Result indicate that in many cases, this approach can boost the fault coverage of circular BIST to match that of conventional parallel BIST approaches while still maintaining a significant advantage in terms of hardware overhead and control complexity View full abstract»

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  • Test methodology for embedded cores which protects intellectual property

    Publication Year: 1997 , Page(s): 2 - 9
    Cited by:  Papers (14)
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    Testing of embedded cores poses a great challenge. These cores cannot be tested in isolation because core I/Os are not directly accessible from ASIC I/Os. A novel test methodology is developed which generates a partial netlist for protection of intellectual property (IP) by performing structural analysis. This partial netlist is used in ASIC level test generation. For the remaining gates of the core, patterns are supplied to test those gates, which can be applied through only core scan chain. Another scheme is developed to select a few I/Os optimally to add boundary scan circuits to improve IP protection View full abstract»

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  • Salvaging test windows in BIST diagnostics

    Publication Year: 1997 , Page(s): 416 - 425
    Cited by:  Papers (13)
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    This paper uses the STUMPS architecture to study the properties of a new diagnostic procedure. According to the old procedure the process stops at the end of each test window to compare the measured signature against its precomputed value. The old procedure also calls for the abandonment of all future test windows after the first failing one is encountered. This is due to the unavailability of expected future test window signatures in the presence of a previously captured error. This paper shows a simple method of salvaging future test windows by adjusting their expected signatures to fit past observed errors. Experiments conducted using this new procedure reveals an improvement of at least one order of magnitude in diagnostic resolution over what has been previously experienced View full abstract»

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  • Testing embedded cores using partial isolation rings

    Publication Year: 1997 , Page(s): 10 - 16
    Cited by:  Papers (48)  |  Patents (10)
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    Intellectual property cores pose a significant test challenge. The core supplier may not give any information about the internal logic of the core, but simply provide a set of test vectors for the core which guarantees a particular fault coverage. If the core is embedded within a larger design, then the problem is how to apply the specified test vectors to the core and how to test the user-defined logic around the core. A simple and fast solution is to place a full isolation ring (i.e., boundary scan) around the core, however, the area and performance overhead for this may not be acceptable in many applications. This paper presents a systematic method for designing a partial isolation ring that provides the same fault coverage as a full isolation ring, but avoids adding MUXes on critical timing paths and reduces area overhead. Efficient ATPG techniques are used to analyze the user-defined logic surrounding the core and identify a maximal set of core inputs and outputs (that includes the critical timing paths) that do not need to be included in the partial isolation ring. Several different partial isolation ring selection strategies that vary in computational complexity are described. Experimental results are shown comparing the different strategies View full abstract»

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  • A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures

    Publication Year: 1997 , Page(s): 80 - 85
    Cited by:  Papers (24)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB)  

    In this paper, we propose a novel IC diagnosis approach, based on probabilistic differential quiescent current (IDDQ) signatures. Unlike the previous diagnosis approaches using current, this approach, using the maximum likelihood estimation, provides a solid framework allowing to quantify its robustness with respect to current measurement variations. The differential nature of the signatures allows to treat subthreshold leakage currents as a noise source. Results are provided showing the robustness of the approach. The applicability of the approach on embedded logic is also briefly discussed View full abstract»

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  • Robust sequential fault testing of iterative logic arrays

    Publication Year: 1997 , Page(s): 238 - 244
    Cited by:  Papers (2)
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    Technology advances provide today the capability of integrating large Iterative Logic Arrays (ILAs) in the same chip. Traditional combinational fault models are not sufficient to detect all failures in CMOS ILAs. Robust test generation for sequential faults in ILAs has not been considered in the literature. Two-pattern tests for sequential fault detection in ILAs can be invalidated either at the cell level due to arbitrary delays inside the cells or at the array level due to the appearance of glitches at the cell inputs. A realistic sequential fault model for any type of ILA is introduced. The fault model along with algorithms for the elimination of glitches in one-dimensional ILAs provide a comprehensive methodology for robust sequential fault testing. C-testability and linear-testability are seeked to provide efficient test sets. Results of the implementation of the method on a comprehensive set of benchmark one-dimensional ILAs are provided. Test complexity and thus test cost is greatly reduced compared to exhaustive two-pattern testing proposed in the past for sequential fault testing in ILAs View full abstract»

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  • Using ATPG for clock rules checking in complex scan designs

    Publication Year: 1997 , Page(s): 130 - 136
    Cited by:  Papers (5)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (704 KB)  

    Structured Design-For-Testability (DFT) employs automated Design-Rules-Checking (DRC) to ensure a design is testable and test patterns can be produced using Automated Test Pattern Generation (ATPG). Central to DRC are ATPG-related clock rules. This paper defines a robust set of clock rules and their implementation for scan designs. It then extends clock-rule-violation detection beyond test requirements, which provides fast clock verification early in the design cycle, complementing the more complex and slower timing tools. Results on a large microprocessor design show the applicability of ATPG-based timing verification View full abstract»

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  • Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS

    Publication Year: 1997 , Page(s): 177 - 182
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB)  

    It is important to predict noise at the early stages of a top down design. In this paper, we propose a methodology to model phase noise or jitter, a key specification for phase-locked loops, using a mixed-signal hardware description language, and to simulate the effects of catastrophic faults on the phase jitter at the behavioral level. In contrast to existing approaches which either require dedicated noise simulators or postpone noise and fault simulation to the transistor level, we have successfully demonstrated that noise in a voltage-controlled oscillator, power supply noise, and their effects on the overall phase jitter within a faulty phase locked loop can be modeled and simulated earlier on at the behavioral level. Our simulation results are consistent with experimentally verified, theoretical predictions View full abstract»

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  • A high-level synthesis approach to design of fault-tolerant systems

    Publication Year: 1997 , Page(s): 356 - 361
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (616 KB)  

    Fault-tolerance in embedded systems is a requirement of increasing importance; solutions must achieve a balance between performances and costs that was not usually requested in design of more classical fault-tolerant applications and that involves as a consequence new approaches. A design technique is here proposed supporting fault-tolerance of hardware modules in complex hardware-software systems, fault-tolerance requirements for each hardware-mapped process are specified in terms of time constraints and of relative priorities, and a high-level synthesis methodology allowing to design - for each process - a processor capable of supporting both the nominal execution of the process itself in a fault-free environment and simultaneous execution of a reconfigured pair of processes in a fault-affected environment is defined Performances of the scheduling algorithm, allowing to achieve reconfiguration with minimum resource increase and within the required limits of speed degradation, are evaluated on some relevant instances of algorithms discussed in current literature on high-level synthesis View full abstract»

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  • SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation

    Publication Year: 1997 , Page(s): 274 - 281
    Cited by:  Papers (12)  |  Patents (1)
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    We propose three synchronous parallel algorithms for scalable parallel test set partitioned fault simulation. The algorithms are based on a new two-stage approach to parallelizing fault simulation for sequential VLSI circuits in which the test set is partitioned among the available processors, The test set partitioning inherent in the algorithms overcomes the good circuit logic simulation bottleneck that exists in traditional fault partitioned approaches to parallel fault simulation. The implementations were done on a shared memory multiprocessor and on a network of workstations. Two of the algorithms show a small degree of pessimism in a few cases, with respect to the fault coverage as compared with a uniprocessor run, while the third algorithm provides the same results as in a uniprocessor run. All algorithms provide excellent speedups and perform much better than a traditional fault partitioned approach, on both shared and distributed memory parallel platforms View full abstract»

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  • Fast algorithms for static compaction of sequential circuit test vectors

    Publication Year: 1997 , Page(s): 188 - 195
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a small set of states, and some states are frequently re-visited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and sufficient conditions are met for them. The techniques require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in significant compactions very quickly for circuits that have many revisited states View full abstract»

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  • A practical approach to instruction-based test generation for functional modules of VLSI processors

    Publication Year: 1997 , Page(s): 17 - 22
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB)  

    This paper presents a practical approach to functional test pattern generation for gate level faults in functional modules of VLSI processors. Test patterns are generated by constrained test generation and translated to functional test patterns, each of which is a sequence of instructions. In this paper, the outline of instruction-based test generation system, ALPS, is given first, and then constrained test generation is described in detail. Finally, the result of practical application to a VLSI processor is given to illustrate the effectiveness of our approach View full abstract»

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  • Fault coverage of a long random test sequence estimated from a short simulation

    Publication Year: 1997 , Page(s): 391 - 398
    Cited by:  Papers (1)
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    Forecasting the fault coverage of a long random test sequence from the results obtained from the simulation of a short test sequence looks like an inaccessible dream. As a matter of fact, a short test sequence detects mainly easy to detect faults, while the test length required for a fault coverage close to 1 depends mainly (almost only) on the most difficult faults. A new 2-parameter model, linking the fault coverage to the test length, was proposed recently. Although these parameters are very difficult to obtain, they can be roughly estimated from a relatively short simulation. According to a previous comment, the results can not be accurate. However, they are more accurate that ones obtained from other models proposed in the literature View full abstract»

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  • Determination of coherence errors in ADC spectral domain testing

    Publication Year: 1997 , Page(s): 308 - 313
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    Coherence of the input and clock frequencies input to an analog-to-digital converter (ADC) during the spectral domain based effective number of bits (ENOB) test is desirable in order to achieve reproducible results without resorting to windowing functions. Impact of these errors on the ENOB test of an ADC is first discussed. A simple model of an ADC used to test the effect of coherence is given. Then this paper presents a method to detect and measure these coherence errors. The ADC model is used to demonstrate this method. Experimental results applied to a 10-bit 40 MSPS converter with a 10 MHz input sinewave are also presented View full abstract»

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  • A new approach for testing artificial neural networks

    Publication Year: 1997 , Page(s): 245 - 250
    Cited by:  Papers (1)
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    This paper presents progress on a new and novel testing approach for detecting interconnection deletion faults in electronic implementations of artificial neural networks (ANNs). The testing approach is based on an unusual transient behavior manifested by faulted ANNs showing better apparent performance than fault-free ANNs, when neurons are operated with low activation function gains. The result presented in this paper improves on prior results by requiring fewer test patterns View full abstract»

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  • ATPG for scan chain latches and flip-flops

    Publication Year: 1997 , Page(s): 364 - 369
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (492 KB)  

    A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while checking their response. Such tests guarantee the detection of all detectable combinational defects inside the bistable elements. The algorithm is implemented by modifying an existing stuck-at combinational test pattern generator. The number of test patterns generated by the new program is comparable to the number of traditional stuck-at patterns. This shows that this approach is practical for large circuits View full abstract»

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  • Incremental logic rectification

    Publication Year: 1997 , Page(s): 143 - 149
    Cited by:  Papers (4)
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    We address the problem of rectifying an incorrect combinational circuit against a given specification. Based on the symbolic BDD techniques, we consider the rectification process as a sequence of partial corrections. Each partial correction reduces the size of the input vector set producing error responses. Compared with existing approaches, this approach is more general, and able to handle circuits with multiple errors. We also formulate the necessary and sufficient condition of general single-gate correction to achieve better results for some circuits with a single error. To handle larger circuits, we develop a hybrid approach that makes use of the information of structural correspondence between specification and implementation. Experimental results on industrial examples as well as ISCAS85 benchmark circuits are presented to show the effectiveness of our approach View full abstract»

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  • An on-line testable UART implemented using IFIS

    Publication Year: 1997 , Page(s): 344 - 349
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (524 KB)  

    This paper presents the design of a complex integrated circuit realised through a novel on-line test methodology. The circuit and its exact conventional equivalent both have been realised in FPGA technology. As such it represents one of the more complex designs realised to date using on-line test approaches. The approach used IFIS (If it Fails It Stops) incorporates dual-rail coding of individual data and a handshaking protocol, which substantially simplifies the detection of failure. Details of the IFIS methodology are given. The IFIS and conventional re-design of a commercial UART are reported, focusing on methodological issues as well as size and speed. Output traces are shown for the IFIS UART on FPGA operating under fault-free conditions and with deliberate failures injected View full abstract»

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  • EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage

    Publication Year: 1997 , Page(s): 329 - 335
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    We describe an approach to test generation for synchronous sequential circuits that accepts a given test sequence T and targets only faults that could not be detected by the test generation procedure that produced T (hard to detect faults). For every fault f that remains undetected by T, the proposed procedure extracts from T a small number of subsequences (two or three subsequences) that can be combined to form a test sequence for f. It then adds these sequences, if found, to T. By exploring only test sequences that can be extracted from T, a restricted search space for test generation is obtained, and it can be thoroughly explored. Experimental results show that non-trivial numbers of additional faults can be detected by using the proposed procedure to extend a given test sequence T View full abstract»

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  • Switch-level modeling of feedback faults using global oscillation control

    Publication Year: 1997 , Page(s): 117 - 122
    Cited by:  Papers (1)
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    To simulate the effects of feedback bridging faults accurately, it is necessary to take into account both the conflict between signals of opposite logic values and the oscillation or asynchronous behavior induced by global feedback loops. This papers presents a method for detecting and processing global feedback dynamically in logic simulation. The problem of asynchronous behavior in feedback paths with an even number of inversions is solved by breaking the feedback and evaluating the possible stable states separately. Simulation experiments show that the uncertainty in fault diagnosis can be significantly reduced by incorporating the proposed technique for feedback analysis View full abstract»

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  • Assessing SRAM test coverage for sub-micron CMOS technologies

    Publication Year: 1997 , Page(s): 24 - 30
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (600 KB)  

    This paper proposes a realistic memory fault probability model which predicts the probabilities of memory fault classes for a given process technology. Physical defects in the memory array are classified into five functional fault classes, which are stuck-at, stuck-open, transition, coupling, and data retention faults. Finally, the memory fault coverages of the known memory test algorithms are evaluated based on their functional fault class coverages View full abstract»

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