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Specification, Verification and Design Languages, 2008. FDL 2008. Forum on

Date 23-25 Sept. 2008

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Displaying Results 1 - 25 of 57
  • [Title page]

    Page(s): I
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    Freely Available from IEEE
  • [Copyright notice]

    Page(s): II
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    Freely Available from IEEE
  • Welcome to FDL’08

    Page(s): III
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    Freely Available from IEEE
  • FDL Committees

    Page(s): IV - VI
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    Freely Available from IEEE
  • Table of contents

    Page(s): VII - X
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  • Index of authors

    Page(s): XI
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    Freely Available from IEEE
  • Symbolic quasi-static scheduling of actor-oriented SystemC models

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (495 KB) |  | HTML iconHTML  

    In this paper, we propose a quasi-static scheduling (QSS) method applicable to actor-oriented SystemC designs. QSS determines a schedule where several static schedules are combined in a dynamic schedule to reduce runtime overhead. This is done by performing as much static scheduling as possible at compile time, and only treating data-dependent control flow as runtime decision. Our approach improves known quasi-static approaches in a way that it is directly applicable to real world designs, and has less restrictions on the underlying model. The effectiveness of the approach based on symbolic computation is demonstrated by scheduling a SystemC design of a network packet filter. View full abstract»

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  • Modelling Program-State Machines in SystemC™

    Page(s): 7 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB) |  | HTML iconHTML  

    The Program-State Machine (PSM) unifies the concepts of hierarchical concurrent finite-state machines, dataflow graphs and imperative programming languages in a single model of computation. It is used as the foundation of the SpecC System Level Design Language. This paper demonstrates the obstacles and proposes an implementation of the PSM model of computation using SystemC. It is shown that this implementation overcomes some fundamental obstacles when using SystemC for System Level Design. Furthermore, we show the applicability of our PSM implementation by porting a JPEG encoder design originally implemented in SpecC. A comparison of model execution time is very promising and shows that our proposed approach is competitive with a native SpecC model execution. View full abstract»

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  • Extending SystemC clocks to model SoC

    Page(s): 13 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (399 KB) |  | HTML iconHTML  

    SystemC provides a clock with a limited interface. While it is generally not an issue for the modeling or the verification of a single IP, this limited API can hardly help modeling a large SoC using multiple dynamic clocks for power reasons. The SystemC clock is implemented with using the global timed event queue of the simulation kernel which can become a bottleneck of the simulation. Poor clock performances are thus discouraging using them like in OSCI/TLM models, but at the expense of complex timing management. This paper presents an extended clock API which also provides a scalable timing mechanism for the modules so that they donpsilat need to be aware of the clock period. These clocks both improve the simulation speed and ease the modeling while preserving ascending compatibility. View full abstract»

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  • Efficient modelling and simulation of embedded software multi-tasking using SystemC and OSSS

    Page(s): 19 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (435 KB) |  | HTML iconHTML  

    Since the software part in todaypsilas designs is increasingly important, the impact of platform decisions with respect to the hardware and the software infrastructure (OS, scheduler, priorities, mapping) has to be explored in early design phases. In this paper, we present an extension of the existing SystemCtrade-based OSSS design flow regarding software multi-tasking in system models. The simulation of the OSSS software run-time model supports different scheduling policies, as well as efficient timing annotations, and deadlines. Inter-task communication is modelled via user-defined shared objects. The impact of timing annotation granularity on the achievable simulation performance is studied. As a result, a lazy synchronisation scheme is proposed, that is based on omitting SystemC time synchronisations, that do not have observable effects on the application model. View full abstract»

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  • Connecting SystemC-AMS models with OSCI TLM 2.0 models using temporal decoupling

    Page(s): 25 - 30
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (471 KB) |  | HTML iconHTML  

    Recent additions to the system modelling language SystemC, namely SystemC-AMS and OSCI TLM 2.0, provide more efficient ways to model systems within their respective domains. However, most of todaypsilas embedded systems are usually heterogeneous, requiring some way to connect and simulate models from different domains. In this paper we present a first approach on connecting SystemC-AMS models and TLM 2.0 models using temporal decoupling. We show how certain properties of the involved models of computation can be exploited to maintain high simulation performance. Using an example to show the feasibility of our approach, we could also observe a certain tradeoff between simulation performance and accuracy. Further on, we discuss semantical issues and decisions that have to be made, when models are connected. As these decisions are typically application-driven, we propose a converter structure that keeps converters simple but also provides ways to model application-specific behaviour. View full abstract»

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  • Towards a common HW/SW interface-centric and component-oriented specification and design methodology

    Page(s): 31 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (472 KB) |  | HTML iconHTML  

    In the scope of initial discussions about a standard OMG IDL-to-VHDL language mapping, we present some requirements and propose a configurable mapping. We demonstrate the advantages of a common component-oriented approach to specify HW and SW interfaces compared to previous object-oriented approaches. Our proposition is based on a family of hardware interfaces enabling to represent various interaction semantics and mapping configurations. Our approach is illustrated through the CORBA component model (CCM). View full abstract»

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  • A latency, preemption and data transfer accurate adaptive Transaction Level Model for efficient simulation of pipelined buses

    Page(s): 37 - 42
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (385 KB) |  | HTML iconHTML  

    Transaction level modeling (TLM) and efficient system level simulation have become invaluable tools for analysis and design of state of the art embedded systems. Abstraction level of the models used in simulation depends on the use case and there is a strong trade off between simulation speed and accuracy. In traditional TLM, the abstraction level of the models is fixed during simulation. Often, except for some intervals during simulation, the models are too accurate for the simulation scenario, negatively affecting simulation speed. In this paper we propose an adaptive TLM for pipelined buses with an accuracy that dynamically adapts to the simulation scenario. The proposed model accurately models latency, preemption and data transfer timings. Considering complex timing properties of pipelined buses this level of accuracy is only available in much slower, cycle accurate models. We have developed an adaptive model of the AMBA AHB protocol in SystemC based on the OSCI TLM 2 standard. Comparison of our model with existing non-adaptive models and analysis with data traffic in real world embedded systems clearly show the improvement in performance without the loss of accuracy. View full abstract»

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  • Application - platform performance modeling and evaluation

    Page(s): 43 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (956 KB) |  | HTML iconHTML  

    Increasing number of concurrent applications in future mobile devices will be based on parallel heterogeneous multiprocessor system-on-chip platforms using network-on-chip communication to achieve scalability. In this paper we describe a performance modeling and simulation approach to explore efficiently the application-platform solution/design space at system-level. The application behavior is abstracted to workload models that are mapped onto performance models of the execution platform for transaction level simulation. The approach provides separation of application and platform through service-oriented modeling. The experimentation of the approach in virtual network computing and mobile video player case studies is presented. View full abstract»

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  • A SystemC-based framework for modeling and simulation of networked embedded systems

    Page(s): 49 - 54
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (431 KB) |  | HTML iconHTML  

    Next-generation networked embedded systems pose new challenges in the design and simulation domains. System design choices may affect the network behavior and network design choices may impact on the system design. For this reason, it is important -at the early stages of the design flow- to model and simulate not only the system under design, but also the heterogeneous networked environment in which it operates. For this purpose, we have exploited a modeling language traditionally used for System design -SystemC- to build a system/network simulator named SystemC Network Simulation Library (SCNSL). This library allows to model network scenarios in which different kinds of nodes, or nodes described at different abstraction levels, interact together. The use of SystemC as unique tool has the advantage that HW, SW, and network can be jointly designed, validated and refined. As a case study, the proposed tool has been used to simulate a sensor network application and it has been compared with NS-2, a well-known network simulator; SCNSL shows nearly two-order-magnitude speed up with TLM modeling and about the same performance as NS-2 with a mixed TLM/RTL scenario. The simulator is partially available to the community at http://sourceforge.net/projects/scnsl/. View full abstract»

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  • A SYSTEMC language extension for high-level reconfiguration modelling

    Page(s): 55 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB) |  | HTML iconHTML  

    The ongoing trend towards development of parallel software and the increased flexibility of state-of-the-art programmable logic devices are currently converging in the field of reconfigurable hardware. On the other hand there is the traditional hardware market, with its increasingly short development cycles, which is mainly driven by high-level prototyping of products. This paper presents a library for modelling reconfiguration in the leading high-level system description language SystemC combining IP reuse and high-level modelling with reconfiguration. Details on the underlying simulation engine are given, which allows safe disabling and re-enabling of all process types without altering the kernel. Novel control statements and internal techniques that allow safe usage of process controlling in conjunction with standard SystemC language constructs are presented. A real world case study using the presented library proves its applicability. View full abstract»

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  • Specification of adaptive HW/SW systems in SystemC

    Page(s): 61 - 66
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (374 KB) |  | HTML iconHTML  

    This paper proposes a SystemC-based specification methodology of adaptive embedded systems to be implemented on a platform including one or more processors, thus supporting the execution of embedded software, and digital hardware with capabilities of partial dynamic reconfiguration (DRHW). For it, it proposes the collaboration of two specification methodologies: HetSC and OSSS+R. The main issues for the integration of these specification methodologies are addressed. This includes how to install and use them together, which is the structure of the specification, how adaptivity is specified for SW and DRHW implementation, and the syntactical and semanticual issues related to the MoC interface implicit in their connection. View full abstract»

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  • Towards compilation of streaming programs into FPGA hardware

    Page(s): 67 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB) |  | HTML iconHTML  

    There is an increasing need for automated conversion of high-level design descriptions into hardware. We present a flow that converts a software application written in the Brook streaming language into a hardware description targeting FPGAs. We use a combination of our source-to-source compiler and a commercial C2H behavioral synthesis compiler. Our approach results in a significant through-put increase compared to software and ordinary C2H results (up to 8.9X and 4.3X, respectively). The throughput can be further increased by using more hardware resources to exploit data parallelism available in streaming applications. View full abstract»

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  • Methodologies for high-level modelling and evaluation in the automotive domain

    Page(s): 73 - 77
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (323 KB) |  | HTML iconHTML  

    As design complexity increases, todaypsilas HDL-based design flows push the capabilities of designers and tools to the limit. In recent years, ambitious efforts at increasing the abstraction level of formal design languages have been presented in order to overcome these limitations. Nevertheless, certain parts of all systems still have to be described in detail. Unfortunately, even small analog parts can slow down a global system simulation significantly. It is therefore necessary to generate abstract models with reduced but adequate result accuracy for these ldquobottleneckrdquo components. This paper presents a novel approach to the automated generation and evaluation of abstract behavioural models for automotive applications. Our methodology aims at achieving a convincing speedup in global system verification by accelerating the transient simulation of the crucial analog and mixed-signal components. The speedup results not only from an increased level of abstraction but also from a fast generation of circuit equations without the need for numerical integration. The approach is able to handle nonlinear circuits by employing piecewise linear models. The use of a SystemC interface will allow effortless integration into manifold simulation environments. View full abstract»

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  • Designing highly parameterized hardware using xHDL

    Page(s): 78 - 83
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (716 KB) |  | HTML iconHTML  

    Current submicron technologies allow a very high degree of integration, resulting in incredibly complex designs implemented in a single chip. The task of the hardware designer is every day more complicated since the data and parameters involved in a design are wider and with increasing complexity in the interfaces. Modular design is needed to deal with these large, regular and repetitive structures. With this purpose the meta-language xHDL was conceived, providing flexible and friendly mechanisms for component parameterization, customization, instantiation and interconnection. In this paper two case studies will be analyzed in depth to illustrate the advantages of using xHDL. Based on the lessons learnt when specifying the case studies the meta-language has been extended to deal with new advanced features such as instantiation of external VHDL components and automatic generation of libraries of components. View full abstract»

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  • Formal transformation of a KPN specification to a GALS implementation

    Page(s): 84 - 89
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (390 KB) |  | HTML iconHTML  

    Kahn process networks (KPNs) provide a model of computation for streaming audio, video and various multimedia applications. However, the KPN model consists of unbounded FIFOs between these communicating processes which need to be realized by other means. Application of a design transformation process to a KPN style specification towards a Globally asynchronous locally synchronous (GALS) implementation is one way of achieving this. Furthermore, this transformation process needs to preserve the Kahn principle. In this paper, our main contribution is the presentation of one such refinement based design transformation that preserves the Kahn principle. We present correctness preserving transformation towards a lookup-based architecture where the communication between processes is facilitated by a shared on-chip lookup storage structure. This refinement methodology is generic, and various alternate schemes of GALS implementation can be derived. View full abstract»

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  • A sigma-delta bandpass ADC modelling in superconducting RSFQ technology with VHDL-AMS

    Page(s): 90 - 93
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (578 KB) |  | HTML iconHTML  

    This paper presents a sigma delta bandpass ADC modelling based on RSFQ (rapid single flux quantum) technology with VHDL-AMS. A Josephson junction model is proposed and simulated based on RCSJ electrical model. Each ADC element is dissociated and simulated to validate its behaviour. We assimilate ADCpsilas comparator which is composed by two Josehpson junctions to an ideal rectangular pulses generator. Pulses duration is directly a physical parameter obtained by technology. We give relations between ADC performance (SNR) to the comparator SFQ pulses form and duration with normalized physical parameters. View full abstract»

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  • VHDL-AMS implementation of a numerical ballistic CNT model for logic circuit simulation

    Page(s): 94 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (452 KB) |  | HTML iconHTML  

    This paper introduces a novel numerical carbon nanotube transistor (CNT) modelling approach which brings in a flexible and efficient cubic spline non-linear approximation of the non-equilibrium mobile charge density. The spline algorithm creates a rapid and accurate solution of the numerical relationship between the charge density and the self-consistent voltage, which leads to the speed-up of deriving the current through the channel without losing much accuracy. This modelling method also allows the flexibility of choosing different cubic spline intervals which may affect the performance of the model, but it is still capable of obtaining an acceleration of more than a 100 times while maintaining the accuracy within less than 1.5% normalised RMS error compared with previous reported theoretical modelling approach. The model has been proved working as transistors in a logic inverter implemented using VHDL-AMS and simulated in SystemVision, which shows the availability of implementing a circuit-level simulators with our proposed model. Additionally, although this model is originally based on the ideal ballistic transport characteristics, it shows good flexibility that the extension with numbers of non-ballistic features are certainly acceptable. View full abstract»

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  • SystemC-AMS modeling of an electromechanical harvester of vibration energy

    Page(s): 99 - 104
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (468 KB) |  | HTML iconHTML  

    This paper presents the results of modeling of a mixed non-linear, strongly coupled and multidomain electromechanical system designed to scavenge the energy of ambient vibrations and to generate an electrical supply for an embedded microsystem. The system is operating in three domains: purely mechanical (the resonator), coupled electromechanical (electrostatic transducer associated with the moving mass) and electrical circuit, including switches, diodes and linear electrical components. Although only linear networks can be properly modeled in SystemC-AMS, we propose a technique allowing modeling of electrical networks including non-linear components (diodes) as well as time-varying capacitors. The whole system was modeled using two solvers of SystemC-AMS simultaneously: the one allowing TDF (timed data flow) modeling and the one allowing LIN ELEC (linear electrical) circuit analysis. The modeling results are compared with VHDL-AMS and Matlab Simulink models. View full abstract»

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  • Integrated requirement evaluation of non-functional system-on-chip properties

    Page(s): 105 - 110
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (447 KB) |  | HTML iconHTML  

    In this paper, a novel design and analysis methodology for simulation-based determination of non-functional properties of a system design, like performance, power consumption and temperature is proposed. For simulation acceleration and handling of complexity issues, the design flow includes automated abstraction of component functionality. Specified platform attributes as dynamic power management and formally declared temporal input stimuli are automatically transformed to non-functional SystemC models. The framework implements the ability for automated online and offline analysis of non-functional system-on-chip properties. View full abstract»

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