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2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN)

Date 24-27 June 2008

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Displaying Results 1 - 25 of 78
  • Message from the conference general chair and coordinator

    Publication Year: 2008, Page(s): i
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  • Message from the DCCS program chair

    Publication Year: 2008, Page(s): ii
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  • Message from the PDS program chair

    Publication Year: 2008, Page(s): iii
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  • William C. Carter Award

    Publication Year: 2008, Page(s): iv
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  • DSN 2008 organizers

    Publication Year: 2008, Page(s): v
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  • DSN 2008 Steering Committee

    Publication Year: 2008, Page(s): vi
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  • DCCS 2008 Program Committee

    Publication Year: 2008, Page(s):vii - viii
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  • DCCS reviewers

    Publication Year: 2008, Page(s):ix - x
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  • PDS 2008 Program Committee

    Publication Year: 2008, Page(s): xi
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  • PDS reviewers

    Publication Year: 2008, Page(s): xii
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  • DSN 2008 subCommittees

    Publication Year: 2008, Page(s): xiii
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  • Citation information

    Publication Year: 2008, Page(s): xiv
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  • Dependability on the last frontier

    Publication Year: 2008, Page(s): xv
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  • Automotive Enhanced Vision Systems - Issues arising from placing users in the loop

    Publication Year: 2008, Page(s): xvi
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  • Coverage of a microarchitecture-level fault check regimen in a superscalar processor

    Publication Year: 2008, Page(s):1 - 10
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2668 KB) | HTML iconHTML

    Conventional processor fault tolerance based on time/space redundancy is robust but prohibitively expensive for commodity processors. This paper explores an unconventional approach to designing a cost-effective fault-tolerant superscalar processor. The idea is to engage a regimen of microarchitecture-level fault checks. A few simple microarchitecture-level fault checks can detect many arbitrary fa... View full abstract»

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  • Analysis and solutions to issue queue process variation

    Publication Year: 2008, Page(s):11 - 21
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3017 KB) | HTML iconHTML

    The last few years have witnessed an unprecedented explosion in transistor densities. Diminutive feature sizes have enabled microprocessor designers to break the billion-transistors per chip mark. However various new reliability challenges such as process variation (PV) have emerged that can no longer be ignored by chip designers. In this paper, we provide a comprehensive analysis of the effects o... View full abstract»

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  • Trace-based microarchitecture-level diagnosis of permanent hardware faults

    Publication Year: 2008, Page(s):22 - 31
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2333 KB) | HTML iconHTML

    As devices continue to scale, future shipped hardware will likely fail due to in-the-field hardware faults. As traditional redundancy-based hardware reliability solutions that tackle these faults will be too expensive to be broadly deployable, recent research has focused on low-overhead reliability solutions. One approach is to employ low-overhead (ldquoalways-onrdquo) detection techniques that ca... View full abstract»

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  • A study of cognitive resilience in a JPEG compressor

    Publication Year: 2008, Page(s):32 - 41
    Cited by:  Papers (16)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (943 KB) | HTML iconHTML

    Many classes of applications are inherently tolerant to errors. One such class are applications designed for a human end user, where the capabilities of the human cognitive system (cognitive resilience) may compensate some of the errors produced by the application. We present a methodology to automatically distinguish between tolerable errors in imaging applications which can be handled by the hum... View full abstract»

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  • Scheduling algorithms for unpredictably heterogeneous CMP architectures

    Publication Year: 2008, Page(s):42 - 51
    Cited by:  Papers (9)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (586 KB) | HTML iconHTML

    In future large-scale multi-core microprocessors, hard errors and process variations will create dynamic heterogeneity, causing performance and power characteristics to differ among the cores in an unanticipated manner. Under this scenario, naive assignments of applications to cores degraded by various faults and variations may result in large performance losses and power inefficiencies. We propos... View full abstract»

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  • Automated duplicate detection for bug tracking systems

    Publication Year: 2008, Page(s):52 - 61
    Cited by:  Papers (51)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (438 KB) | HTML iconHTML

    Bug tracking systems are important tools that guide the maintenance activities of software developers. The utility of these systems is hampered by an excessive number of duplicate bug reports-in some projects as many as a quarter of all reports are duplicates. Developers must manually identify duplicate bug reports, but this identification process is time-consuming and exacerbates the already high... View full abstract»

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  • Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor

    Publication Year: 2008, Page(s):62 - 69
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2035 KB) | HTML iconHTML

    The SPARC64 V microprocessor is designed for use in high-reliability, large-scale unix servers. In addition to implementing ECC for large SRAM arrays, the SPARC64 V microprocessor incorporates error detection and recovery mechanisms for processor logic circuits and smaller SRAM arrays. The effectiveness of these error recovery mechanisms was validated via accelerated neutron testing of Fujitsupsil... View full abstract»

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  • Using likely program invariants to detect hardware errors

    Publication Year: 2008, Page(s):70 - 79
    Cited by:  Papers (36)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2479 KB) | HTML iconHTML

    In the near future, hardware is expected to become increasingly vulnerable to faults due to continuously decreasing feature size. Software-level symptoms have previously been used to detect permanent hardware faults. However, they can not detect a small fraction of faults, which may lead to silent data corruptions(SDCs). In this paper, we present a system that uses invariants to improve the covera... View full abstract»

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  • Detouring: Translating software to circumvent hard faults in simple cores

    Publication Year: 2008, Page(s):80 - 89
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (487 KB) | HTML iconHTML

    CMOS technology trends are leading to an increasing incidence of hard (permanent) faults in processors. These faults may be introduced at fabrication or occur in the field. Whereas high-performance processor cores have enough redundancy to tolerate many of these faults, the simple, low-power cores that are attractive for multicore chips do not. We propose Detouring, a software-based scheme for tol... View full abstract»

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  • Towards assessing the security of DBMS configurations

    Publication Year: 2008, Page(s):90 - 95
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (333 KB) | HTML iconHTML

    Database management systems (DBMS) have a long tradition in high security. Several mechanisms needed to protect data have been proposed/consolidated in the database arena. However, the effectiveness of those mechanisms is very dependent on the actual configuration chosen by the database administrator. Tuning a large database is quite complex and achieving high security is a very difficult task tha... View full abstract»

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  • Experiences with formal specification of fault-tolerant file systems

    Publication Year: 2008, Page(s):96 - 101
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (952 KB) | HTML iconHTML

    Fault-tolerant, replicated file systems are a crucial component of todaypsilas data centers. Despite their huge complexity, these systems are typically specified only in brief prose, which makes them difficult to reason about or verify. This paper describes the authorspsila experience using formal methods to improve our understanding of and confidence in the behavior of replicated file systems. We... View full abstract»

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