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Circuits and Systems and TAISA Conference, 2008. NEWCAS-TAISA 2008. 2008 Joint 6th International IEEE Northeast Workshop on

Date 22-25 June 2008

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Displaying Results 1 - 25 of 106
  • A spread-spectrum clock generator with dual-voltage controlled oscillator

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB) |  | HTML iconHTML  

    This paper proposes a spread spectrum clock generator (SSCG) for EMI reduction. The SSCG circuit utilizes a dual-voltage controlled oscillator based on the regular integer-N PLL. The circuit has been simulated in 0.18 mum CMOS technology. A 40 KHz triangular waveform is used for frequency modulation. The spectrum spread ratio ranges from 0.125% to 1%. The peak power reduction is 16 dB. View full abstract»

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  • Phase-frequency synthesis using PLL-networks

    Page(s): 5 - 8
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (615 KB) |  | HTML iconHTML  

    Conventional phase locked loop (PLL)-networks used for phase synthesis lack accurate frequency controllability. We describe a novel phase-frequency synthesizer architecture based on coupled-PLLs suitable for communication systems. We also present the phase noise analysis of the proposed architecture and demonstrate its superior phase noise performance compared with conventional coupled-PLLs. View full abstract»

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  • A wide band CMOS differential voltage-controlled ring oscillator

    Page(s): 9 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1306 KB) |  | HTML iconHTML  

    This paper presents the design of a wide band two-stage CMOS voltage-controlled ring oscillator based on the Maneatis cell. The VCO is designed for a frequency synthesizer module that generates local oscillation (LO) frequencies over a large bandwidth, targeting a multi-band acquisition system. The goal is a wide operating frequency tuning range of 400 MHz - 1.4 GHz in the VCO with low power consumption, -80 dBc/Hz@600 KHz phase-noise performance and a good linearity for the frequency and control voltage characteristics. Simulation results verify the theoretical development and measurement results validate the design. The symmetric load transistor operation region controls the frequency behavior achieved by the VCO, which shows a monotonic relation with the control voltage when the loads are operated in saturation. The prototype chip was fabricated using a 0.18mum IBM CMOS technology. View full abstract»

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  • Design of a wide tuning range VCO using an active inductor

    Page(s): 13 - 16
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (515 KB) |  | HTML iconHTML  

    This paper presents a wide tuning range CMOS voltage controlled oscillator suitable for radio frequency operation. The major advantage of this structure is the absence of on-chip inductor, thus reducing significantly the chip area. Measurements results using a 0.35 mum CMOS process from AMS have shown a wide tuning range of 84% of the 915 MHz central frequency and a phase noise around -90 dBc/Hz at 500 kHz offset from the carrier. The power consumption is reduced to less than 10 mW from a 3.3 V supply. View full abstract»

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  • Wide-division-range high-speed fully programmable frequency divider

    Page(s): 17 - 20
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1729 KB) |  | HTML iconHTML  

    This paper presents the design and implementation of an all-programmable frequency divider with an ultra-wide division range for use in phase-locked loops. The proposed divider uses a fully modular architecture and dynamic logic - implemented in TSMC 0.18 mum - and can divide input frequencies up to 7.55 GHz by any ratio between 8 and 255 while consuming 11 mW from a 1.8 V power supply. The divider compares very favorably to other implementations reported in literature in terms of division range and frequency of operation. View full abstract»

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  • A recursive multifunction circuit for leading-digit detection and comparison

    Page(s): 21 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (225 KB) |  | HTML iconHTML  

    It is known that fast, fully combinational leading-digit detector circuits can be generated efficiently by recognizing their inherent hierarchical structure. It is shown herein that this structure is not only hierarchical, but also recursive. This recursivity fully defines a minimal-complexity circuit, thus guaranteeing optimal circuit synthesis. Such a circuit having an N-bit operand generates all output bits with log2(N) combinational stages. It also makes possible a recursive parameterizable description in VHDL or other hardware description languages supporting recursion. For standard cell generation, it is amenable to efficient, automatic recursive routing. Furthermore, the same recursive structure can serve as the basis of other useful arithmetic functions, such as a fast comparator (log2(N) stages). Therefore, such a multifunction circuit could be employed in the design of fast, low-complexity arithmetic-logic units (ALUs) inside microprocessors, digital signal processors, or application-specific system-on-chip (SoC) designs. View full abstract»

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  • Implementation of a configurable router for embedded network-on-chip support in FPGAs

    Page(s): 25 - 28
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (223 KB) |  | HTML iconHTML  

    This paper presents the architecture and implementation of a configurable router intended for embedded network-on-chip support within field-programmable gate arrays. The router supports five network topologies and utilizes a dual-crossbar arrangement to reduce resource utilization. The router has been implemented in an Altera Stratix chip and in a 0.18-mum standard-cell process. For the routing and switching logic, the dual-crossbar arrangement is more area-efficient than a full crossbar, averaging a reduction of 24% in FPGA logic and 22% in gates for custom implementation. The average operating frequency of the dual-crossbar design is 123 MHz in FPGA logic and 340 MHz for custom implementation. Custom NoC support in an FPGA would therefore have adequate performance relative to components implemented in fully-programmable logic. View full abstract»

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  • A method for efficient mapping and reliable routing for NoC architectures with minimum bandwidth and area

    Page(s): 29 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (289 KB) |  | HTML iconHTML  

    Network-on-chip (NoC) is an on-chip communication methodology that has been proposed as an alternative to bus-based communication in order to cope with the increased complexity in embedded designs. This paper presents a method for assigning tasks to nodes in a 2-D mesh, and for determining the nodes positions on the mesh using simulated annealing. The method proposes a new efficient routing algorithm that minimizes blocking while increasing bandwidth throughput. The method is implemented and various benchmarks are attempted. View full abstract»

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  • Multithreading and interprocessor communication in a dual-issue pipelined processor

    Page(s): 33 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (217 KB) |  | HTML iconHTML  

    This paper describes multithreading and interprocessor communication support in a dual-issue pipelined 32-bit processor for prototyping single-chip multiprocessors in programmable logic. Multithreading support includes multiple register contexts and instructions for thread management. Interprocessor communication support includes a ring network interface embedded in the pipelined datapath with instructions for sending and receiving data through the interface. Synthesis results are presented for a multiprocessor system in an Altera Stratix chip, demonstrating that hardware support for eight threads constitutes 18% of the logic in each processor and the ring interface constitutes less than 3% of the logic. View full abstract»

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  • Iterative design method for video processors based on an architecture design language and its application to ELA deinterlacing

    Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (550 KB) |  | HTML iconHTML  

    This paper presents a design methodology for dedicated real-time video processors. The methodology begins with a basic processor that is progressively morphed into a specialized processor through five systematic steps. It differs from standard methodologies for ASIP design which place exclusive emphasis on the extension of the instruction set. The proposed methodology takes a global look at various processor and system considerations. The last step consists of removing unnecessary functionality from the instruction set. The required flexibility is attained by the use of an architectural description language. We use a basic deinterlacing algorithm to demonstrate the effectiveness of the methodology and present details of the various phases of the design process. Using ELA deinterlacing as a benchmark, the final processor uses 20% fewer logic elements, achieves a global acceleration by a factor of 11, and an improvement in area-delay product of 14, with respect to the basic processor. View full abstract»

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  • Implantation study of an analog spiking neural network in an auto-adaptive pacemaker

    Page(s): 41 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (664 KB) |  | HTML iconHTML  

    The goals of this research are to develop an analog spiking neural network so as to improve the performance of biventricular pacemaker (CRT devices). Implantation in silicon uses the analogical neural network approach that requires the development of a technical solution satisfying the requirement of very low energy consumption. Targeting an alternative analog solution in 0.18 mum CMOS technology, this paper presents a new approach in analog spiking neural network for the delay prediction by using a Hebbian learning algorithm. View full abstract»

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  • A charge based sigma delta capacitive sensor for ultrathin polyelectrolyte layer detection

    Page(s): 45 - 48
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB) |  | HTML iconHTML  

    In this paper, we present a hybrid microfluidic/CMOS sensor for lab-on-chip (LoC) applications. This hybrid device features a sigma delta (SigmaDelta) capacitive sensor implemented through 0.18 mum CMOS process, a direct-write microfluidic channel and ultrathin polyelectrolyte layers (PLs). We demonstrate the simulation and experimental results and show the viability of the proposed sensor for molecular detection purposes using chitosan and alginate solutions. View full abstract»

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  • A video stream processor for real-time detection and correction of specular reflections in endoscopic images

    Page(s): 49 - 52
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (522 KB) |  | HTML iconHTML  

    This paper presents the architecture and FPGA implementation of a video processor for detection and correction of specular reflections in endoscopic images by using an inpainting algorithm. Stream processing and parallelism are used to exceed real-time performance on NTSC format video without the need for an external memory. The system was implemented in a XC2VP30 FPGA and uses 91% of available slices. Image quality is significantly enhanced. View full abstract»

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  • Real time Optofluidic Microscopy

    Page(s): 53 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1867 KB) |  | HTML iconHTML  

    This paper demonstrates the design of a two dimensional nanoholes array opto-fluidic microscopy (OFM). Contrary to previous OFM designs, our design captures accurate real-time images of biological samples flowing in a microfluidic channel. In addition, the enhanced design allows us to monitor the flow of micro-organisms by continuously acquiring images with acceptable frame rate. Details of the enhanced OFM structure as well as the analysis that proves its feasibility and simulations that illustrates its advantages are all presented. View full abstract»

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  • Ultra low energy communication protocol for implantable body sensor networks

    Page(s): 57 - 60
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (583 KB) |  | HTML iconHTML  

    Body sensor network (BSN) is a wireless network of implantable and/or wearable smart sensors. They can be deployed in medical applications, such as patients monitoring inside or outside hospital environment, as well as in high performance professional sports and other non human related applications. The size of a sensor node and its power consumption are major challenges in the design of implantable BSNs. The focus of this paper is to propose the definition of a new light weight communications protocol for the BSNs applications using very small sensor nodes supporting ultra low energy consumption. View full abstract»

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  • Complex FIR block adaptive algorithm employing optimal time-varying convergence factors

    Page(s): 61 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (417 KB) |  | HTML iconHTML  

    The Complex Least Mean Square algorithm (Complex LMS) has been widely used in various adaptive filtering applications, e.g. in the wireless communications and biomedical fields, due to its computational simplicity. However, the main drawback of the Complex LMS algorithm is its slow convergence. In addition, the performance is dependent on the choice of the convergence factor or learning rate. In this paper, a novel complex block adaptive algorithm is presented that overcomes the performance limitation of the Complex LMS. The proposed algorithm (Complex OBA-LMS) derives independent time-varying convergence factors for the real and imaginary components of the FIR complex adaptive filter coefficients. Furthermore, the convergence factors are updated at each block iteration. The convergence speed and accuracy of the Complex OBA-LMS algorithm are investigated and compared with the Complex LMS algorithm. Simulation results show that the proposed technique exhibits superior performance at the expense of a modest increase in computational complexity for different training inputs. View full abstract»

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  • On-line memory polynomial predistortion based on the adapted kalman filtering algorithm

    Page(s): 65 - 68
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (718 KB) |  | HTML iconHTML  

    A new adaptive technique for digital predistortion is presented. The proposed method uses the real-time digital processing of baseband signals to compensate the nonlinearities and memory effects in radio-frequency power amplifier. Kalman filtering algorithm with sliding time-window is adapted to track the changes in the PA characteristics. Simulation and measurement results, using digital signal processing, are presented for multicarrier signals to demonstrate the effectiveness of this new approach. View full abstract»

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  • Identification of autoregressive moving average systems from noise-corrupted observations

    Page(s): 69 - 72
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB) |  | HTML iconHTML  

    In this paper, a new scheme for the identification of minimum-phase autoregressive moving average (ARMA) systems from noise-corrupted observations is presented. Analyzing the characteristics of the autocorrelation function (ACF) of the observed data in the presence of noise, a set of equations has been developed which is capable of estimating the AR parameters of the ARMA system as well as the noise variance. In order to estimate the MA parameters, first, a residual signal is obtained by filtering the noisy observations via the estimated AR parameters. Utilizing the estimated noise variance and the AR parameters, a noise-subtraction algorithm is proposed to reduce the effect of noise from the ACF of the residual signal. The MA parameters are then estimated employing the spectral factorization corresponding to the noise-compensated ACF of the residual signal. Computer simulations on different ARMA systems demonstrate a superior identification results in terms of estimation accuracy and consistency even under a heavy noisy condition. View full abstract»

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  • Scheduling of turbo decoding on a multiprocessor platform to manage its processing effort variability

    Page(s): 73 - 76
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (405 KB) |  | HTML iconHTML  

    This paper presents means of mapping and scheduling portions of a wide-band code division multiple access (WCDMA) application on a homogeneous multi processor system-on-chip (MPSoC). We focus on the turbo decoder, which is a computationally intensive part of the application and which presents a significant processing variability. Our model allows deriving and validating a flexible scheduling method for turbo decoding tasks, which is adapted to the variable processing effort required by the decoder. Using a proposed performance model, the efficiency of this scheduling method is demonstrated. A proposed flexible scheduling (FS) method, when compared to a worst case execution time (WCET) scheduling method, allows increasing the number of users from 14 to 29, while keeping an acceptable quality of service, as reflected in a very small degradation of less than 0.15 dB of the decoding gain. View full abstract»

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  • On extracting pitch from noisy speech signals based on spectral and temporal enhancement

    Page(s): 77 - 80
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (598 KB) |  | HTML iconHTML  

    A new pitch extractor based on spectral and temporal enhancement of noisy speech signals is presented in this paper. A discrete cosine transform based modified power spectral subtraction scheme is developed and employed prior to pitch extraction in order to suppress the underlying non-stationary noise. The de-noised speech thus obtained is then passed through an inverse filter, whose parameters are derived from the linear prediction (LP) analysis, yielding an output referred to as the LP residual. Since the LP residual is capable of delivering the knowledge of Glottal Closure instants, exploiting its high correlation property, an average magnitude sum function as well as an average magnitude difference function are introduced. The periodicity property of both the functions is argued to be integrated and an enhanced temporal function is put forward for robust pitch extraction in a multi-talker babble noise scenario. The superior efficacy of the proposed pitch extractor relative to some of the existing ones is confirmed through simulation results using the Keele database. View full abstract»

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  • A power efficient hold-friendly flip-flop

    Page(s): 81 - 84
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (817 KB) |  | HTML iconHTML  

    In this paper a hold-friendly scan flip-flop is introduced whose scan pin hold characteristic has improved while data pin timing and power are left intact. This characteristic helps to resolve scan chain hold problem while meeting the maximum frequency in data path. This solution can reduce the number of buffers inserted in the scan chain to fix hold violations. The new flip-flop can save up to 27% area and 15% power as compared to the usage of normal flip-flops combined with hold-fixing buffers. View full abstract»

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  • Packing-driven sliceable transformation for 3D floorplan designs

    Page(s): 85 - 88
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (402 KB) |  | HTML iconHTML  

    Given a 3D non-slicing floorplan, based on the property of packing-driven ordering in the floorplan, all the blocks can be ordered as a block list. Furthermore, according to the maintenance of a dynamic sliceable floorplan, any 3D non-slicing floorplan can be transformed into a 3D slicing floorplan by shifting the related blocks to minimize the final floorplan volume. The experimental results show the proposed approach is more effective than the modified FTP-1 algorithm. Clearly, the proposed approach can serve as a post-processing phase for other non-slicing floorplan algorithms. View full abstract»

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  • An vector automatic matching system designed for wireless medical telemetry

    Page(s): 89 - 92
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (541 KB) |  | HTML iconHTML  

    A novel adaptive antenna impedance matching system based on vector detection method for medical telemetry is proposed. The system controls a pi matching network tunable components by detecting the antenna complex impedance. The antenna complex impedance is extracted in order to set the proper state configuration of the tunable matching network with basic calculation. Only 10 mus tuning time is required and 30 dB improvement of return loss is obtained. The emitterpsilas power and the receiverpsilas sensitivity can be optimized whatever the perturbations on the wireless link. The whole system has been simulated on a 2.4 GHz ISM emitter. View full abstract»

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  • A 60GHz CMOS RMS power detector for antenna impedance mismatch detection

    Page(s): 93 - 96
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (719 KB) |  | HTML iconHTML  

    This paper presents a RMS power detector in 65 nm CMOS for applications in WPAN 60 GHz band. After presenting the context, the interest of power detection in RF transmitter chain is explained together with some 60 GHz VSWR antenna measurements. Then, a state of the art of the detection techniques is given to justify our architecture choice and the operating principle is detailed. Finally, simulations results are presented which show a linear detection range of 25 dB at 60 GHz. View full abstract»

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  • 3D Hall probe integrated in 0.35 μm CMOS technology for magnetic field pulses measurements

    Page(s): 97 - 100
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (441 KB) |  | HTML iconHTML  

    This paper presents a 3 dimensional magnetometer based on Hall effect sensors integrated without any post processing in a standard low cost 0.35 mum CMOS technology. The system is dedicated to magnetic pulses measurements under a strong static field. Two vertical Hall devices (VHD) are sensitive to the components of the magnetic field oriented in the plane of the chip, while a horizontal Hall device (HHD) is sensitive to the component of the magnetic field orthogonally oriented to the plane of the chip. 3 identical instrumental chains are integrated to perform amplification of the 3 Hall voltages. The system implements a compensation of the static magnetic field and allows to measure magnetic fields pulses with a resolution of 79 muT over a [5 Hz - 1.6 kHz] bandwidth. Pulses are in the range from hundreds of muT to tens of mT in the frequency range from 1 Hz to 10 kHz. The static field is compensated up to 1.5 T. The spatial resolution is 44 mum. The system power consumption has been optimized to 15 mW. View full abstract»

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