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Electronic Packaging Technology & High Density Packaging, 2008. ICEPT-HDP 2008. International Conference on

Date 28-31 July 2008

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Displaying Results 1 - 25 of 232
  • Proceedings, 2008 international conference on electronic packaging technology & high density packaging (ICEPT-HDP 2008)

    Publication Year: 2008 , Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (67 KB)  
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2008 , Page(s): 1
    Save to Project icon | Request Permissions | PDF file iconPDF (63 KB)  
    Freely Available from IEEE
  • Qualification for product development

    Publication Year: 2008 , Page(s): 1 - 12
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (189 KB) |  | HTML iconHTML  

    The aim of qualification is to verify whether a product meets or exceeds the reliability and quality requirements of its intended application. Qualification plays an important role in the process of product development. It can be classified by its specific purpose at different stages of the product development process. In this paper, a new methodology of product qualification is proposed based on physics-of-failure. This methodology consists of: product configuration and material information collection; application requirement information collection; strength limits and margins; failure modes, mechanisms and effects analysis; definition of qualification requirements; qualification test planning; testing; failure analysis and verification; and quality and reliability assessment. This approach to qualification ensures that it successfully addresses the failure mechanisms applicable to the productpsilas specific design, manufacture, and application conditions. View full abstract»

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  • High density 3D integration

    Publication Year: 2008 , Page(s): 1 - 10
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2639 KB) |  | HTML iconHTML  

    This paper discusses the current and future needs in continued CMOS scaling, reviews the status of the transfer and joining (TJ) technology for MCM-D and wafer level 3DI integration, and explores the opportunities of the TJ technology in the realm of the ldquoMore than Moorerdquo era. View full abstract»

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  • A study of thermal performance for the panel base package (PBP™) technology

    Publication Year: 2008 , Page(s): 1 - 5
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1490 KB) |  | HTML iconHTML  

    A new panel base package (PBP) technology that was developed based on the concepts of the wafer level package (WLP) has been proposed in order to obtain the signal fan-out capability for the fine-pitched integrated circuit (IC). In the PBP, the chip is attached to a selected chip carrier, and the volume of IC devices is extended for the redistribution of the original die pads. In this study, the thermal performance of the PBP technology was investigated and discussed through three-dimensional finite element (FE) analysis. In order to compare the thermal performance between conventional WLP and the proposed PBP, the junction temperature of WLP was also recorded through the modified FE model. The results showed that due to the larger packaging size of the PBP structure, the added solder bumps can be used as thermal balls. Moreover, they can effectively reduce the packaging thermal resistance (from 55degC/W to 41degC/W). It is expected that thermal performance could be further improved by applying solder paste between the chip and chip carrier. The study likewise discussed the condition of forced convection and developed the PBP technology for high-density IC devices. In light of the results obtained from this study, we believe in our new PBB technologypsilas great potential for future applications. View full abstract»

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  • FMEA of System-in-Package (SiP) -based Tire Pressure Monitoring System

    Publication Year: 2008 , Page(s): 1 - 6
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (560 KB) |  | HTML iconHTML  

    For transferring R&D efforts into real product manufacturing, proper product reliability qualification is one of the most critical considerations during product development in addition to assembly yield prediction. It is particularly important for automotive electronics because the operating conditions are extremely harsh (e.g. -20degC ~ 105degC) and a number of applications are even related to human safety. Failure mode and effects analysis (FMEA) of SiP-based tire pressure monitoring system (TPMS) is selected in this paper as an illustration of the process for transferring R&D efforts into real product. FMEA is proven as a useful tool in the early design stage to identify any potential design and/or process-related failure modes, corresponding effects, root causes followed by corrective actions. Better quality and reliability, shorter system development time and cost, as well as early identification and elimination of potential failure modes can therefore be achieved. In addition, numerical analysis was performed during the course of FMEA in order to address the potential risks and therefore to provide proper recommendations. View full abstract»

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  • Ultrasonic bonding of polymer microfluidic chips

    Publication Year: 2008 , Page(s): 1 - 5
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (712 KB) |  | HTML iconHTML  

    Bonding is an essential step to enclose microchannels or microchambers in lab-on-a-chip. Ultrasonic bonding was studied as a deformation-free technique to realize high efficiency bonding of microfluidic chips. Based on viscoelastic dissipation theory, the main influential factors of heat generation rate during ultrasonic bonding was theoretically analyzed and numerically calculated using finite element method. According to the results, micro energy directors were designed to concentrate the ultrasonic power and to control the location of the joint. To demonstrate the performance of this bonding method, specially designed PMMA substrates of microfluidic chips were fabricated by means of hot embossing. With the ultrasonic bonding technique, the chips were reliably and hermetically bonded within less than a second. View full abstract»

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  • Mold array package for POP applications

    Publication Year: 2008 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (589 KB) |  | HTML iconHTML  

    The package on package (POP) stacking is getting more and more popular for system in package (SIP) applications. But during the assembly process, the POP had encountered the challenge of packages stacking yield loss, especially when top package and bottom package stacking. The key factors are the mount height of top package, the mold cap of bottom package, and the metallized ball land on the top surface of bottom package. JEDEC JC-11 has defined the rules of two packages stacking. However, the fine pitch package stacking application will meet the process capability limitation, including thinner mold cap, wafer thinning and the lowest wire bond loop height challenges. The POP used the top gate mold chase for the bottom package to expose the metallized ball land on the top side of package which is a dedicated molding tooling. Also, some process are used for solving yield loss issues such as a POP with interposer between top package and bottom package, or a bottom package with pre-mounted the solder ball on chip side ready for top package to attach. Those are customized tooling and not a prevailing tooling that increases the developing cost and timing. To resolve the stacking process yield loss issue, a MAPPOP solution had been revealed for eliminating the limitation between the top and bottom package stacking. The assembly process of mold array package (MAP) for fine pitch BGA has been implemented for MAPPOP applications. In the paper, the package design rules, and assembly process of exposed metallized ball land on the top surface of bottom package had been discussed. Finally the warpage performance and the packaging level reliability had also been discussed and analyzed. View full abstract»

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  • New technologies for advanced high density 3D packaging by using TSV process

    Publication Year: 2008 , Page(s): 1 - 3
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (989 KB) |  | HTML iconHTML  

    There is no question that 3D integration will be the next generation of packaging. This requires new technologies from ultra thin wafer handling to wafer to wafer bonding with 3D inter substrate connections. TSV is a process in which wafers are thinned, stacked and interconnected to significantly improve electrical performance such as signal transmission, interconnect density, reduced power consumption, form factor and manufacturing costs. View full abstract»

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  • Recent progress of ohmic contact on ZnO

    Publication Year: 2008 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (281 KB) |  | HTML iconHTML  

    ZnO as an excellent candidate for UV light emitters, varistors, transparent high-power electronics, surface acoustic wave devices, piezoelectric transducers, and chemical and gas sensors could be integrated in a SiP (system-in-package). The SiP could be a critical part in sensor nodes in a sensor network. Normally, the ZnO device in SiP is fabricated with nanoscale films which can be compatible with other materials and processing in a package. However, despite the great potential for electron and photonic applications, ZnO device fabrication is difficult to obtain good ohmic contact. The low resistance and thermal stable ohmic contacts is critical to realize high-performance ZnO-based devices. In this paper, the recent advances of ohmic contacts on ZnO are analyzed and reviewed. The mechanism of the energy band bending at the interface of the semiconductor and the metal is discussed. The factors of forming good quality ZnO films such as the choice of the substrate and the method to deposit ZnO film, the effect of the contact resistance and thermal stability of ohmic contacts are summarized. View full abstract»

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  • Low-cost high-efficiency 4 channel pluggable parallel optical transceiver using optoelectronic MCM packaging technologies

    Publication Year: 2008 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (406 KB) |  | HTML iconHTML  

    A compact 4times2-channel parallel optical MCM transceiver with data rates up to 3.125 Gb/s per channel was studied for very short reach (VSR) interconnection. The transceiver was based on 1times4 VCSEL and PD arrays of 850 nm wavelength, and a 12-fiber-ribbon as the transmission medium. Greatly relaxed alignment tolerance and high coupling efficiency between optoelectronic (OE) device arrays and fiber arrays were achieved. The eye-diagram at 2.5 Gb/s was measured under 231-1 pseudorandom bit stream (PRBS). View full abstract»

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  • SiP/SoP technology and its implementation

    Publication Year: 2008 , Page(s): 1 - 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (245 KB) |  | HTML iconHTML  

    ldquoSystem-in-packagerdquo(SiP) and ldquosystem-on-packagerdquo (SoP) are different but similar in concepts. SiP and SoP definition were found in many open sources. SoP promises much more technologies and functions over SiP, leads to too many and more complicated research areas, and long time to develop, which could lost patience and interest from industry. Module-in-package(MiP) was proposed as a replacement of SoP for real implementations. View full abstract»

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  • Packaging of polymer based microfluidic systems using low frequency induction heating (LFIH)

    Publication Year: 2008 , Page(s): 1 - 6
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1201 KB) |  | HTML iconHTML  

    Microfluidic systems are being used in more and more areas and the demand for such systems is growing every day. Hence, a cheap and rapid method for sealing these microfluidic platforms which can be used for mass manufacture is needed. In this paper low frequency induction heating (LFIH) is presented as technique for the packaging of polymer based microfluidic systems. Thin metal layers serving as susceptors are introduced between a stack of polymer slides and heated inductively. The generated heat melts the surrounding polymer and creates a bond. Preliminary work reported here has demonstrated such bonds are able to withstand a pressure of up to 590 kPa, that both ferro- and paramagnetic susceptors are suitable for the bonding process, and that even small metal features can be rapidly heated to a temperature of 200degC. View full abstract»

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  • Analysis of the reliability of package-on-package devices manufactured using various underfill methods

    Publication Year: 2008 , Page(s): 1 - 3
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (531 KB) |  | HTML iconHTML  

    As next-generation electronic packages continue to dictate smaller devices and more functionality, package-on-package (POP) configurations have started to gain popularity in the SMT industry. These stacked package devices enable board space savings, simplified system design, enhanced performance, and lower pin count. Although POPs are experiencing rapid growth for certain applications such as mobile handsets, digital cameras, PDAs, and MP3 players, concerns over POP drop test and thermal cycling performance reliability issues have been raised. Recently, the electronics industry has gathered a great deal of POP reliability data to help optimize the POP manufacturing and application process. A number of studies and tests have been conducted to investigate the board-level reliability of POPs in relation to drop test and thermal cycling performance. The test conditions have examined packages manufactured with and without underfill and have also analyzed the impact of different underfill dispensing patterns (i.e. full underfill, cornerbond and edgebond) However, few papers discuss the effects of the underfilling strategy-such as undefilling the bottom component only or underfilling both top and bottom components, or the effects of solder alloy choice on the reliability of POP packaging. In this paper, the effects of underfill dispensing type and POP ball alloy type on the reliability of POP devices during drop testing and thermal cycle testing were evaluated. It was found that both underfill dispensing type and alloy type have a profound effect on POP reliability. The study results revealed that underfilling only the bottom component seems to have no significant contribution to POP drop test reliability. Underfilling both the top and bottom components yields better drop test performance than underfilling only the bottom component. In addition, the SAC105 (98.5%Sn + 1.0%Ag + 0.5%Cu) bump alloy shows better drop test performance than the SAC305 (96.5%Sn + 3.0%Ag + 0.5%Cu) - - alloy. View full abstract»

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  • Meeting thermal performance and reliability challenges for a thermally enhanced ball grid array package (TEBGA)

    Publication Year: 2008 , Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1131 KB) |  | HTML iconHTML  

    For devices with challenging power management requirement, thermally enhanced ball grid array package (TEBGA) offers a good solution, where the device is attached to a heat spreader, usually made of copper, with a thermally conductive epoxy to ensure a good conductive path for heat to escape from the die. The top die surface and bonding wires are covered with an overmolding compound for environmental protection such that heat dissipation is typically limited in that direction. However, TEBGA is not without its unique challenges. In this paper, we present a study on the challenges of meeting the thermal performance and reliability requirements for a ASIC packaged with TEBGA. A localized deformation or ldquodimplerdquo of the TEBGA package is discovered during the package assembly process, where the heat-spreader is noted to have deformed under the die shadow, which results in a circular shaped indentation. This raises concerns about the impact on the thermal performance of the subsequent package to heat sink interface when it is integrated into the system. Solution to this potential problem rests on balancing thermal performance, reducing package stress level & understanding potential long term package reliability. Deformation of the package with each process step will be first described and particular attention will be given to the change of package profile after the die attach process; then a finite element analysis of the stress and deformation of the die attach process is discussed and important parameters affecting the deformation and stress are shown; moreover, a thermal resistance model assessing the thermal budget for this package in a system environment is reviewed and confirmation with numerical analysis & validation by experimental analysis are highlighted; furthermore, an interactive analysis is subsequently performed based on the FEA model for package stress/deformation and thermal resistance model to optimize the packaging solution; finally, b- - alanced solution through this interactive optimization process is summarized and demonstrated in the manufacturing process. View full abstract»

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  • Numerical simulation of the micro-channel heat sink on non-uniform heat source

    Publication Year: 2008 , Page(s): 1 - 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (514 KB) |  | HTML iconHTML  

    In this paper, the different heat source distributions are studied in the micro-channel heat sink (MCHS) cooler. The simulation model is established to analyze the heat distributing and temperature rise of the MCHS with different channel width-dimensions. Uniform and non-uniform heat source are used to offer a constant heat flux, and the total heat flux amount is 270 W. Water is chosen as the coolant for its superior hot properties and the velocity range is from 0.01 m/s to 10 m/s. The results show that tradition type MCHS will be under a low efficiency for cooling a non-uniform heat source. And the non-equal displacement of fins can effective decrease the temperature rise about 10% under the same cooling conditions cooling a non-uniform heat source. We also find that it is impossible to enhance the cooling effect through adding the flow rate if it has surpassed itpsilas limitation. View full abstract»

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  • Heat transfer simulation of nanofluids in micro channel cooler

    Publication Year: 2008 , Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB) |  | HTML iconHTML  

    Since the pioneering work by Tuckerman & Pease, lots of publications about heat sink has been researched in the last decade. Many enhancements are proposed in order to increase the thermal conductivity of micro-channels including nanofluids, special shapes, and two phase flows. The nanofluid is a solid-liquid mixture which is composed of nanoparticles and a basic liquid. In this paper, the nanofluids with suspended multiwalled carbon nanotube and other metallic or nonmetallic particles are compared to enhance the heat transfer performance. The thermal resistance of the heat sink with nanofluids is simulated. View full abstract»

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  • Flip-chip on board packaging of a thermal wind sensor

    Publication Year: 2008 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (646 KB) |  | HTML iconHTML  

    A two dimensional wind sensor was designed, fabricated and packaged on ceramic substrate instead of silicon substrate. The Ti/Pt heater and thermistors were fabricated using single lift-off process. The gold bumps were then sputtered and patterned on the chip using lift-off process again. Correspondingly, the Pb/Sn bumps were fabricated on the FR4 substrate using stencil printing method after metallization. The sensor chip was flip-chip packaged on the FR4 substrate, and the gap was filled with epoxy-based underfill to improve the structure strength and thermal isolation. The wind velocity and direction offsets of the sensor were analyzed and compensated using software and hardware calibration. The packaged sensor was tested in wind tunnel in constant power mode. Both the simulation and test results show that the thermal wind sensor can measure wind speeds up to 10 m/s with an accuracy of 0.5 m/s, and wind direction in a full range of 360deg with a resolution within 5deg. View full abstract»

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  • System-in-package solutions with embedded active and passive components

    Publication Year: 2008 , Page(s): 1 - 2
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (249 KB) |  | HTML iconHTML  

    Future generations of electronic products require further developments of integration and packaging technologies. The reasons for this are higher signal frequencies and the increasing functional density at acceptable costs. With the existing technologies organic substrates with high-density built-up layers with microvias can be produced. On both sides of the substrates, passive and active components can be assembled. The surface demand at the side of a printed circuit board for active components can be reduced to a minimum by the application of CSPs (chip size packages) or flip chips. However a further miniaturization requires a three-dimensional integration of the components. Advanced packages contain stacked chips, which are connected by bond wires with an interposer or a lead frame. Apart from the miniaturization the new applications require signal frequencies of several GHz, which can only be recalled with difficult due to the long bond wires and the extensive connection paths on the printed circuit board. Signal integrity requires connections that are much shorter and impedance-matched. This can be reached by embedded components. Embedding signifies that the conductor is not only located under the embedded components, but also on top of them. This enables to continue three-dimensional packaging on top of the embedded component as well. The component is electrically connected with the upper or lower conducting layer or with both of them, e. g. as it is the case in power ICs with contacts on both sides. The Fraunhofer IZM and the Technical University Berlin jointly develop advanced technologies for embedding of active chips for system-in-package (SiP) applications. The first development was the so-called chip-in-polymer technology, which enables the realization of SiPs as well as printed circuit boards with integrated components. It is based on the embedding of thin chips into built-up layers under the consequent use of printed circuit board technologies (PCB tec- - hnologies). Electrical contacts to the chips are realized by laser-drilled and metallized microvias. View full abstract»

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  • Design advisor for package-on-package (PoP) manufacturing

    Publication Year: 2008 , Page(s): 1 - 7
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (822 KB) |  | HTML iconHTML  

    The needs to integrate devices into portable products with smaller form factor and more functionality have fueled enormous growth of 3D packaging technology. The package-on-package (PoP) is one of the 3D packaging solutions, by which the packaging and assembly houses can achieve a lower cost, faster turn benefits and testing prior to assembly. PoP is a complicated system with multi-layered structure, which induces more manufacturability issues, such as stand-off height issue and top & bottom packages having different types of warpage. In order to reduce R&D cost, achieve fast time-to-market and address most of the manufacturability issues during the development of a new PoP, a design advisor for PoP manufacturing has been developed based on the design for manufacturability (DFM) methodology. The key components of this design advisor are the validated numerical models, comprehensive materials library, design guidelines of PoP packaging and novel finite element analysis (FEA) techniques. With the developed novel FEA techniques for curing process simulation and seamless packaging process simulation, complete numerical models for PoP manufacturing were developed and validated, which can simulate the whole PoP manufacturing processes. The design advisor is easy to use by selecting package geometries, material properties and process parameters. By running the envelope-based design advisor for normal package design or the FEA-based design advisor for special package design, the detailed analysis reports can be generated, including simulation results, design evaluations and recommendations to ensure the first-time success of package design. Therefore, the design advisor can help improve the yield of complex PoP manufacturing processes leading to higher quality and confidence of manufacturing processes, faster time-to-market and lower overall manufacturing cost. View full abstract»

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  • Warpage reduction of package-on-package (PoP) module by material selection & process optimization

    Publication Year: 2008 , Page(s): 1 - 6
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2286 KB) |  | HTML iconHTML  

    The package technology has matured significantly over the past several years, shifting from conventional components and direct board level assembly to chip or package level system integration. Two major commonly used approaches are System-on-Chip (SoC) and System-in-Package (SiP). Package-on-Package (PoP) that integrates logic die in the bottom package and memory die in the top package into a single 3D package is one of the promising SiP solutions. The major advantage of PoP packaging is that the top and bottom packages, which are usually designed with FBGA and PBGA package formats, can be tested individually before they are assembled. The yield loss of the whole PoP module can be reduced significantly. However, due to the Coefficient of Thermal Expansion (CTE) mismatch and the stiffness mismatch exist among EMC, substrate and silicon chip, warpages on both top and bottom packages are often observed. Large warpage could cause solder joint open failure and substrate delamination, leading to the electrical connection failure of the assembled module. Theoretically, three approaches can be used to solve the warpage issue of two BGA packages contained in a PoP module: package design, material selection and process optimization. Developing a new package or changing the existing design usually involves many efforts and needs long cycle time, which can not meet the needs of competitive microelectronics industry. The material selection and process optimization are often adopted by industry to achieve the goal of shortening time to market. In this paper, Finite Element (FE) simulation is performed firstly. The CTE of epoxy molding compound (EMC) is found to make an important contribution to the warpage of PoP. The guideline for materials selection is proposed. Based on this guideline, one type of "Green" EMC is selected. Material properties of EMC including filler content, curing degree, CTE and Tg are characterized with thermo-gravimetric analysis (TGA), differential scannin- - g calorimetry (DSC) and thermo-mechanical analysis (TMA) respectively. The effect of the material properties and the post mold curing (PMC) process on the warpage behavior of FBGA package is investigated. Shadow moire system is employed to characterize the warpage of the molded block and signal units. View full abstract»

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  • A new process to fabricate cavities in Pyrex7740 glass for high density packaging of micro-system

    Publication Year: 2008 , Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1176 KB) |  | HTML iconHTML  

    In the domain of manufacturing and packaging of micro-system, the Pyrex7740 glass is a widely-used material since its coefficient of thermal expansion is similar to that of silicon, and its good optical performance for biosensors and optical sensors. But the use of Pyrex7740 glass is limited for its isotropic etching characteristic of tradition micro-machining. In this paper, we present a new process to fabricate deep grooves in Pyrex7740 glass. The process is based on the anodic bonding, and it uses the Si substrate as the mold for forming the shape of the cavity. Finally the cavities were formed by the atmospheric pressure after the special heat treatment. The Pyrex7740 glass with cavities could be used for high density packaging of micro-system by anodic bonding or adhesive bonding. The approach of fabricating deep cavities in Pyrex7740 glass is a key technology, which has seldom studied before. We have experimentally verified the feasibility of this new process. First of all, we fabricated the array of desired shape of cavities on silicon substrate by wet etching or dry etching. It is much easier to get the precise shape on the silicon substrate by micro machining than in Pyrex7740 glass. In our experiment, we had chosen several different side length of the square as a pattern. Then we bonded the Pyrex7740 glass and the silicon substrate together under the vacuum environment by anodic bonding. After that twice heat treatments were taken to the bonding wafer. One was to form the Pyrex7740 glass into desired shape by the silicon mold with the temperature up to the softening point. Another was to release thermal stress of the anodic bonding and the first heat treatment. The placement of the wafer during the heat treatment must be taken attention to. Finally, the bonding wafer with cavities was finished for the high density packaging of micro-system. View full abstract»

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  • DPA tests on SiP device

    Publication Year: 2008 , Page(s): 1 - 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1270 KB) |  | HTML iconHTML  

    The reliability of multi-dice in package was studied in this paper; DPA tests were operated on qualified devices to distribute early failure from overstress failure. Then factorial experiments manipulated on early failure samples for failure analysis. Comparing the C-SAM images before and after a series reliability tests, the reliability of SiP devices was confirmed. View full abstract»

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  • Ultrasonic features in wire bonding and thermosonic flip chip

    Publication Year: 2008 , Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (821 KB) |  | HTML iconHTML  

    Driving voltage and current signals of piezoceramic transducer (PZT) were measured directly by designing circuits from ultrasonic generator and using a data acquisition software system. Input impedance and power of PZT were investigated by using Root mean square (RMS) calculation. Vibration driven by high frequency was tested by laser Doppler vibrometer (PSV-400-M2). Thermosonic bonding features were observed by scanning electron microscope (JSM-6360LV). Results show that the input power of bonding is lower than that of no load. The input impedance of bonding is greater than that of no load. Nonlinear phase, plastic flow and expansion period, and strengthening process were shown in impedance and power curves. The ultrasonic power is proportion to vibration displacement driven by the power, and greater displacements driven by high-power result in welding failure phenomena, such as crack, break, and peel off in wedge bonding,. For thermosonic flip chip bonding, the high power decreases position precision of bonding or results in slippage and rotation phenomena of bumps. To improve reliability and precision of thermosonic bonding, the low ultrasonic power should be chosen. View full abstract»

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  • Development of three-dimensional multichip module based on embedded substrate with multiple interconnections

    Publication Year: 2008 , Page(s): 1 - 6
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1348 KB) |  | HTML iconHTML  

    A new type of 3D multichip module (3D-MCM) for wireless sensor network was developed based on a kind of embedded FR-4 substrate for the wireless sensor network, in which FCOB (flip-chip on board), COB (chip on board), BGA (ball grid array) technologies, wirebonding and flip-chip interconnection technologies were combined together. The PBGA device and bare die were hybrid-integrated on the embedded multi-layer FR-4 substrate. By solder ball placement and reflow the BGA was formed at the bottom of 3D-MCM, and solder balls with different melting points were used for initial and final vertical interconnections for the sake of compatibility of all levels interconnections of BGA by reflow soldering. The application of embedded substrate solved the problem that the top surface of the encapsulated chip overtops the solder balls in the condition that the chip was assembled in the same side of substrate with BGA. The thermal management was conducted and the thermal related reliability of 3D-MCM were simulated and evaluated respectively. This kind of packaging structure satisfies the electrical performance and thermal requirement, and meets the challenge of minimization, high reliability and low cost of the package design for the wireless network. View full abstract»

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