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Architecture for Networking and Communications systems, 2006. ANCS 2006. ACM/IEEE Symposium on

Date 3-5 Dec. 2006

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Displaying Results 1 - 19 of 19
  • A proposed architecture for the GENI backbone platform

    Publication Year: 2006, Page(s):1 - 10
    Cited by:  Papers (5)  |  Patents (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB) | HTML iconHTML

    The GENI Project (global environment for network innovation) is a major NSF-sponsored initiative that seeks to create a national research facility to enable experimental deployment of innovative new network architectures on a sufficient scale to enable realistic evaluation. One key component of the GENI system will be the GENI backbone platform (GBP) that provides the resources needed to allow mul... View full abstract»

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  • Towards an efficient switch architecture for high-radix switches

    Publication Year: 2006, Page(s):11 - 20
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (241 KB) | HTML iconHTML

    The interconnection network plays a key role in the overall performance achieved by high performance computing systems, also contributing an increasing fraction of its cost and power consumption. Current trends in interconnection network technology suggest that high-radix switches will be preferred as networks will become smaller (in terms of switch count) with the associated savings in packet lat... View full abstract»

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  • A practical fast parallel routing architecture for Clos networks

    Publication Year: 2006, Page(s):21 - 30
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (259 KB) | HTML iconHTML

    Clos networks are an important class of switching networks due to their modular structure and much lower cost compared with crossbars. For routing I/O permutations of Clos networks, sequential routing algorithms are too slow, and all known parallel algorithms are not practical. We present the algorithm-hardware codesign of a unified fast parallel routing architecture called distributed pipeline ro... View full abstract»

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  • Design of a web switch in a reconfigurable platform

    Publication Year: 2006, Page(s):31 - 40
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (250 KB) | HTML iconHTML

    The increase of the web traffic has created the need for web switches that are able to balance the traffic to the server farms based on their contents (e.g. layer 7 switching). In this paper we present a web switch implemented in a multiprocessor reconfigurable platform augmented with hardware co-processors. The system supports the TCP splicing scheme to accelerate the routing of the packets by fo... View full abstract»

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  • Packet classification using coarse-grained tuple spaces

    Publication Year: 2006, Page(s):41 - 50
    Cited by:  Papers (2)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (295 KB) | HTML iconHTML

    While the problem of high performance packet classification has received a great deal of attention in recent years, the research community has yet to develop algorithmic methods that can overcome the drawbacks of TCAM-based solutions. This paper introduces a hybrid approach, which partitions the filter set into subsets that are easy to search efficiently. The partitioning strategy groups filters t... View full abstract»

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  • CAMP

    Publication Year: 2006, Page(s):51 - 60
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (311 KB) | HTML iconHTML

    A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been proposed, which delivers very high lookup and update throughput. These architectures often use a pipeline of embedded memories, where each stage stores a single or set of levels of the lookup trie. A stream of lookup requests a... View full abstract»

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  • Fast packet classification using bloom filters

    Publication Year: 2006, Page(s):61 - 70
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (295 KB) | HTML iconHTML

    Ternary content addressable memory (TCAM), although widely used for general packet classification, is an expensive and high power-consuming device. Algorithmic solutions which rely on commodity memory chips are relatively inexpensive and power-efficient but have not been able to match the generality and performance of TCAMs. Therefore, the development of fast and power-efficient algorithmic packet... View full abstract»

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  • Efficient memory utilization on network processors for deep packet inspection

    Publication Year: 2006, Page(s):71 - 80
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (322 KB) | HTML iconHTML

    Deep Packet Inspection (DPI) refers to examining both packet header and payload to look for predefined patterns, which is essential for network security, intrusion detection and content-aware switch etc. The increasing line speed and expanding pattern sets make DPI a challenging task. Network Processors (NPs) are chosen to perform DPI due to their packet processing performance and programmability.... View full abstract»

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  • Advanced algorithms for fast and scalable deep packet inspection

    Publication Year: 2006, Page(s):81 - 92
    Cited by:  Papers (15)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (289 KB) | HTML iconHTML

    Modern deep packet inspection systems use regular expressions to define various patterns of interest in network data streams. Deterministic finite automata (DFA) are commonly used to parse regular expressions. DFAs are fast, but can require prohibitively large amounts of memory for patterns arising in network applications. Traditional DFA table compression only slightly reduces the memory required... View full abstract»

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  • Fast and memory-efficient regular expression matching for deep packet inspection

    Publication Year: 2006, Page(s):93 - 102
    Cited by:  Papers (15)  |  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (339 KB) | HTML iconHTML

    Packet content scanning at high speed has become extremely important due to its applications in network security, network monitoring, HTTP load balancing, etc. In content scanning, the packet payload is compared against a set of patterns specified as regular expressions. In this paper, we first show that memory requirements using traditional methods are prohibitively high for many patterns used in... View full abstract»

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  • An effective network processor design framework - using multi-objective evolutionary algorithms and object oriented techniques to optimise the intel IXP1200 network processor

    Publication Year: 2006, Page(s):103 - 112
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (182 KB) | HTML iconHTML

    In this paper we present a framework for design space exploration of a network processor, that incorporates parameterisation, power and cost analysis. This method utilises multi-objective evolutionary algorithms and object oriented analysis and design. Using this approach an engineer specifies certain hard and soft performance requirements for a multi-processor system, and allows it to be generate... View full abstract»

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  • A methodology for evaluating runtime support in network processors

    Publication Year: 2006, Page(s):113 - 122
    Cited by:  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (865 KB) | HTML iconHTML

    Modern network processor systems require the ability to adapt their processing capabilities at runtime to changes in network traffic. Traditionally, network processor applications have been optimized for a single static workload scenario, but recently several approaches for run-time adaptation have been proposed. Comparing these approaches and developing novel run-time support algorithms is diffic... View full abstract»

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  • High-throughput sketch update on a low-power stream processor

    Publication Year: 2006, Page(s):123 - 132
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (571 KB) | HTML iconHTML

    Sketch algorithms are widely used for many networking applications, such as identifying frequent items, top-k flows, and traffic anomalies. This paper explores the implementation of the Count-Min sketch update using Indexed SRF accesses on a SIMD stream processor (Imagine). Both the sketch data structure and the packet stream are modeled as streams, and in-lane accesses to the stream register file... View full abstract»

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  • Symerton--using virtualization to accelerate packet processing

    Publication Year: 2006, Page(s):133 - 142
    Cited by:  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB) | HTML iconHTML

    The complexity of packet-processing applications continues to grow, with encryption, compression, and XML processing becoming common on packet-processing devices at the edge of enterprise and service provider networks. While performance remains a key differentiator for these devices, the complexity and rate of change in the supported applications has made general-purpose platforms an attractive al... View full abstract»

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  • Sequence-preserving adaptive load balancers

    Publication Year: 2006, Page(s):143 - 152
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (260 KB) | HTML iconHTML

    Load balancing in packet-switched networks is a task of ever-growing importance. Network traffic properties, such as the Zipf-like flow length distribution and bursty transmission patterns, and requirements on packet ordering or stable flow mapping, make it a particularly difficult and complex task, needing adaptive heuristic solutions. In this paper, we present two main contributions: Firstly, we... View full abstract»

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  • Localized asynchronous packet scheduling for buffered crossbar switches

    Publication Year: 2006, Page(s):153 - 162
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (193 KB) | HTML iconHTML

    In such a switch, besides normal input queues and output queues, a small buffer is associated with each crosspoint. Due to the introduction of crosspoint buffers, output and input contention is eliminated, and the scheduling process for buffered crossbar switches is greatly simplified. Moreover, crosspoint buffers enable the switch to work in an asynchronous mode and easily schedule and transmit v... View full abstract»

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  • Scalable network-based buffer overflow attack detection

    Publication Year: 2006, Page(s):163 - 172
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (175 KB) | HTML iconHTML

    Buffer overflow attack is the main attack method that most if not all existing malicious worms use to propagate themselves from machine to machine. Although a great deal of research has been invested in defense mechanisms against buffer overflow attack, most of them require modifications to the network applications and/or the platforms that host them. Being an extension work of CTCP, this paper pr... View full abstract»

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  • WormTerminator

    Publication Year: 2006, Page(s):173 - 182
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (199 KB) | HTML iconHTML

    The fast spreading worm is becoming one of the most serious threats to today's networked information systems. A fast spreading worm could infect hundreds of thousands of hosts within a few minutes. In order to stop a fast spreading worm, we need the capability to detect and contain worms automatically in real-time. While signature based worm detection and containment are effective in detecting and... View full abstract»

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  • Packet pre-filtering for network intrusion detection

    Publication Year: 2006, Page(s):183 - 192
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (237 KB) | HTML iconHTML

    As intrusion detection systems (IDS) utilize more complex syntax to efficiently describe complex attacks, their processing requirements increase rapidly. Hardware and, even more, software platforms face difficulties in keeping up with the computationally intensive IDS tasks, and face overheads that can substantially diminish performance. In this paper we introduce a packet pre-filtering approach a... View full abstract»

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