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1964 Proceedings of the Fifth Annual Symposium on Switching Circuit Theory and Logical Design

11-13 Nov. 1964

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Displaying Results 1 - 25 of 28
  • [Front cover]

    Publication Year: 1964, Page(s): C1
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    Freely Available from IEEE
  • Table of contents

    Publication Year: 1964, Page(s): c2
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    Freely Available from IEEE
  • Foreword

    Publication Year: 1964, Page(s): c3
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    Freely Available from IEEE
  • Ideas of asynchronous feedback networks

    Publication Year: 1964, Page(s):4 - 11
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (887 KB)

    This paper presents an extension of the basic concepts established by Robert McNaughton and David Muller in the field of asynchronous feedback networks. The ideas developed herein are the results of adapting common logical functions in a manner that simplifies the overall design of asynchronous systems. The prime objecttive is to overcome a weakness common to both of the aforementioned concepts, t... View full abstract»

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  • New techniques for designing speed independent control logic

    Publication Year: 1964, Page(s):12 - 29
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2099 KB)

    A speed independent circuit has the property that the relative speed of operation of the various logic elements does not affect the over-all behavior of the circuit. Such circuits have properties which are of particular importance in the design of reliable asynchronous circuits. An Arithmetic Control for a digital computer is one type of logic which can profitably use these characteristics. The de... View full abstract»

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  • Antiparallel control logic

    Publication Year: 1964, Page(s):30 - 43
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1705 KB)

    The inherent problems of data transmission in a strictly feedforward line have been discussed in the literature. In such a line, where the stored data are indexed forward by control pulses moving in a direction away from the data source, if time variations exist in the delays of successive stages then there is always a nonzero probability that two successive control pulses will eventually appear a... View full abstract»

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  • A census finite automata

    Publication Year: 1964, Page(s):44 - 46
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (289 KB)

    Closed form expressions are obtained for enumerating the non-equivalent finite automata under serveral definitions of equivalence. Algorithms are presented for determining the number of connected automata and automata with a distinguished initial state. Useful lower bounds and asymptotic results are obtained. View full abstract»

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  • Turing machine recognizers for general rewriting systems

    Publication Year: 1964, Page(s):47 - 56
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1051 KB)

    The notion of structural descriptions of sentences generated by context-free grammars is generalized to include structural descriptions of derivations in general rewriting systems (GRS's). A structural description is represented by a canonical member of the set of derivations having the same structural description. View full abstract»

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  • Mapping of languages by two-tape devices

    Publication Year: 1964, Page(s):57 - 67
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    First Page of the Article
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  • On formalisms for turing machines

    Publication Year: 1964, Page(s):68 - 75
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    First Page of the Article
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  • On n-type finite state acceptors

    Publication Year: 1964, Page(s):76 - 81
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (753 KB)

    Certain properties of three variants of the multi-tape automata of Rabin and Scott are proved. Closure properties of the defined sets of n-tuples are found, and the nature of projections of the defined sets of n-tuples on one coordinate is studied. Some necessary conditions for acceptance are derived, and a characterization of the sets of n-tuples defined by non-deterministic n-tape automata is fo... View full abstract»

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  • Computational complexity of recursive sequnces

    Publication Year: 1964, Page(s):82 - 90
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1123 KB)

    In this paper we investigate how numbers, functions, and sequences can be classified according to their computational complexity. The computational complexity is measured by how fast the number or function can be computed by a multitape computer (Turing machine). It is shown that by means of this measure the computational complexity of numbers and functions can be submitted to rigorous mathematica... View full abstract»

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  • A lower bound RADO's sigma function for binary turing machines

    Publication Year: 1964, Page(s):91 - 94
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (378 KB)

    In this note we show how to construct some simply-configured N-state binary Turing machines that will start on a blank tape and eventually halt after printing a very large number of ones. The number of ones produced by these machines can be expressed analytically in terms of functional difference equation. The latter expression furnishes the best lower bound presently known for Rado's noncomputabl... View full abstract»

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  • Fault detecting experiments for sequential circuits

    Publication Year: 1964, Page(s):95 - 110
    Cited by:  Papers (151)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2188 KB)

    This paper describes the design of experimental procedures for determining whether or not a sequential switching circuit is operating in accordance with a given state-table description. These procedures are particularly easy to apply when the given state table is reduced, strongly-connected, and has a distinguishing sequence, and when the actual circuit has no more states than the given table. The... View full abstract»

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  • Hazard detection in combinational and sequential switching circuits

    Publication Year: 1964, Page(s):111 - 120
    Cited by:  Papers (17)
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  • Derivation of optimum test sequencies for sequential machines

    Publication Year: 1964, Page(s):121 - 132
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1098 KB)

    A technique is presented for deriving the shortest sequence of input symbols which must be applied to a sequential machine to guarantee that no fault from a set {p} exists within the machine. Flow tables are used to describe the machine for which a test is desired as well as all defective machines into which it is transformed by the faults of {p}. The set of flow tables is combined into a single c... View full abstract»

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  • Topological constraints on interconnection-limited logic

    Publication Year: 1964, Page(s):133 - 137
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    Consideration is given to the manner and extent to which propagation delay and terminal packing factors may constrain the interconnection of modules making up large digital network. When formulated in graph-theoretical terms these considerations give rise to the problem of finding linear graphs with a maximum number, n, of nodes for a given degree, d, and diameter, k--a generalization of the probl... View full abstract»

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  • Some new results on the analysis and reliabilty of large polyfunctional nets

    Publication Year: 1964, Page(s):138 - 148
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1392 KB)

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  • On the minimum stage realization of switching functions using logic gates with limited fan-in

    Publication Year: 1964, Page(s):149 - 155
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (794 KB)

    In this paper a method is presented for reducing the number of stages of logic in the realization of an arbitrary Boolean function when an upper bound exists on the fan-in at each gate. A procedure for obtaining the minimum stage realization of the function in sum of products form is first developed. The use of factoring to reduce the number of stages below this minimum is then described. View full abstract»

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  • Reducing variable dependency in combinational circuits

    Publication Year: 1964, Page(s):156 - 164
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (965 KB)

    The problem of encoding inputs to an n-input, 2-output combinational circuit so as to reduce the number of variables upon which the two output functions depend is considered in this paper. It is assumed that the number of input conditions (n-vectors) which must produce each output state is given. It is clear that for each mapping of n-vectors into output status a different pair of output functions... View full abstract»

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  • A diagrammatic approach to multi-level logic synthesis

    Publication Year: 1964, Page(s):165 - 173
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    A diagrammatic approach to the problem of synthesizing multi-level logic functions is presented. It has the advantage of giving a visual interpretation to such abstract concepts as fan-in, levels of logic, decomposition, and two-level forms. View full abstract»

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  • Implication techniques for Bollean functions

    Publication Year: 1964, Page(s):174 - 182
    Cited by:  Papers (2)
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    This paper presents several uses of the logical connective of implication to problems of interest in switching theory. The implications which hold among the prime implicants of a function are examined. A new set of necessary and sufficient conditions for determining essential prime implicants and a rapid approximate method for obtaining minimal sums are included. View full abstract»

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  • A reduction technique for prime implicant tables

    Publication Year: 1964, Page(s):183 - 191
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (999 KB)

    Solving prime implicant tables is greatly facilitated by reduction techniques such as row dominance, column dominance and essential row selection. This paper presents a new reduction technique which is operable on any otherwise irreducible table having a column covered by two rows. View full abstract»

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  • On the application of pair algebra to automata theory

    Publication Year: 1964, Page(s):192 - 196
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    In this paper, we define and discuss generalizations of partition pairs on sequential machines. The object of these generalizations is to suggest a unified approach to problems of information flow and machine structure. View full abstract»

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  • On the linearity of sequential machines

    Publication Year: 1964, Page(s):197 - 208
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1317 KB)

    This paper presents a method for determining, from the flow table of a sequential machine, whether the machine is linearly realizable using the minimum number of unit delay elements. The method is an extension of a previously presented method for autonomous machines. A linearity algorithm is presented for each of two cases: a) where the output is given and is to be linear, and b) where the output ... View full abstract»

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