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On-Line Testing Symposium, 2008. IOLTS '08. 14th IEEE International

Date 7-9 July 2008

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  • [Front cover]

    Publication Year: 2008 , Page(s): C1
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  • [Title page i]

    Publication Year: 2008 , Page(s): i
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  • [Title page iii]

    Publication Year: 2008 , Page(s): iii
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  • [Copyright notice]

    Publication Year: 2008 , Page(s): iv
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  • Table of contents

    Publication Year: 2008 , Page(s): v - ix
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  • Message from General Chair(s)

    Publication Year: 2008 , Page(s): x
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  • IOLTS 2008 Committees

    Publication Year: 2008 , Page(s): xi
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  • Program Committee

    Publication Year: 2008 , Page(s): xii
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  • Test Technology Technical Council

    Publication Year: 2008 , Page(s): xiii - xv
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  • Test Technology Educational Program (TTEP) 2008 Full-Day Tutorial

    Publication Year: 2008 , Page(s): xvi - xvii
    Request Permissions | Click to expandAbstract | PDF file iconPDF (181 KB)  

    Provides an abstract for each of the presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • On-Line Failure Detection and Confinement in Caches

    Publication Year: 2008 , Page(s): 3 - 9
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (274 KB) |  | HTML iconHTML  

    Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which increases in-the-field error rate due to both latent defects and actual errors. As a consequence, there is an increasing need for continuous on-line testing techniques to cope with hard errors in the field. Similarly, those techniques are needed for detecting soft errors in logic, whose error rate is e... View full abstract»

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  • An Enhanced Logic BIST Architecture for Online Testing

    Publication Year: 2008 , Page(s): 10 - 15
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (331 KB) |  | HTML iconHTML  

    The objective of using logic BIST for online and periodic testing is to identify defects, like opens, resulting from the wear and tear of the circuit. We have shown that existing test sets have a low coverage for open defects located in scan flip-flops, even though such defects may affect functional operation. Existing Logic BIST structures suffer from the same limitations. A novel Logic BIST arch... View full abstract»

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  • Design Techniques for Bit-Parallel Galois Field Multipliers with On-Line Single Error Correction and Double Error Detection

    Publication Year: 2008 , Page(s): 16 - 21
    Request Permissions | Click to expandAbstract | PDF file iconPDF (255 KB) |  | HTML iconHTML  

    Error correction is an effective way to mitigate fault attacks in cryptographic hardware. It is also an effective solution to soft errors in deep sub-micron technologies. To this end, we present a systematic method for designing single error correcting (SEC) and double error detecting (DED) finite field (Galoisfield) multipliers over GF(2m). The detection and correction are done on-line... View full abstract»

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  • Verification and Analysis of Self-Checking Properties through ATPG

    Publication Year: 2008 , Page(s): 25 - 30
    Cited by:  Papers (6)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (742 KB) |  | HTML iconHTML  

    Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient errors during system operation are no longer restricted to memories but also affect random logic, and a robust design becomes mandatory to ensure a reliable system operation. Self-checking circuits rely on redundancy to dete... View full abstract»

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  • Physical Demonstration of Polymorphic Self-Checking Circuits

    Publication Year: 2008 , Page(s): 31 - 36
    Cited by:  Papers (7)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (394 KB) |  | HTML iconHTML  

    Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and u... View full abstract»

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  • New Linear SEC-DED Codes with Reduced Triple Bit Error Miscorrection Probability

    Publication Year: 2008 , Page(s): 37 - 42
    Cited by:  Papers (16)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    This paper solves the problem of minimizing triple bit error miscorrection for single-error-correcting, double-error-detecting codes (SEC-DED codes) which are used to protect all kinds of memory against errors. A lower bound for triple bit error miscorrection for the widely used class of odd-weight column codes is derived and actual codes which are very close to that theoretical bound are presente... View full abstract»

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  • Special Session 1: Radiation Hardening Techniques

    Publication Year: 2008 , Page(s): 43 - 44
    Request Permissions | Click to expandAbstract | PDF file iconPDF (154 KB)  

    First Page of the Article
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  • Soft Error Protection Techniques

    Publication Year: 2008 , Page(s): 45
    Request Permissions | Click to expandAbstract | PDF file iconPDF (113 KB)  

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  • Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS

    Publication Year: 2008 , Page(s): 46 - 48
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (236 KB) |  | HTML iconHTML  

    This paper reviews recent experimental confirmations that the intrinsic radiation robustness of commercial CMOS technologies naturally improves with the down-scaling. When additionally using innovative design techniques, it becomes now possible to assure that performance and radiation-hardness are both met. An illustration is given with an original nano-power and radiation-hardened 8 Mb SRAM desig... View full abstract»

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  • Soft Error Rates of Hardened Sequentials utilizing Local Redundancy

    Publication Year: 2008 , Page(s): 49 - 50
    Cited by:  Papers (7)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (218 KB)  

    Process scaling is well know to increase overall chip-level soft error rates (SER) if no additional mitigation techniques are applied [Seifert04]. The purpose of this study is to summarize recent investigations conducted by the author to characterize the SER benefits and limitations of one particular SER mitigation technique: radiation hardened sequentials that utilize local redundancy. The studie... View full abstract»

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  • False Error Study of On-line Soft Error Detection Mechanisms

    Publication Year: 2008 , Page(s): 53 - 58
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (326 KB) |  | HTML iconHTML  

    With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the doub... View full abstract»

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  • Integrating Scan Design and Soft Error Correction in Low-Power Applications

    Publication Year: 2008 , Page(s): 59 - 64
    Cited by:  Papers (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (529 KB) |  | HTML iconHTML  

    Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random logic is in the order of the number of SRAM cells on chips only a few years ago. Often latches are clock gated and have to retain their states during longer periods. Moreover, miniaturization has led to elevated susceptibili... View full abstract»

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  • A Built-In Self-Test Scheme for Soft Error Rate Characterization

    Publication Year: 2008 , Page(s): 65 - 70
    Cited by:  Papers (8)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (406 KB) |  | HTML iconHTML  

    Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. Soft error rate (SER) measurement, expressed as number of failures encountered per billion hours of device operation, is time consuming and involves significant test cost. The cost stems from having to connect a device-under-test to a tester f... View full abstract»

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  • Budget-Dependent Control-Flow Error Detection

    Publication Year: 2008 , Page(s): 73 - 78
    Cited by:  Papers (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (249 KB) |  | HTML iconHTML  

    The problem of detection of control flow errors in software has been studied extensively in literature and many detection techniques have been proposed. These techniques typically have high memory and performance overheads and hence are unusable for real-time embedded systems which have tight memory and performance budgets. This paper presents two algorithms by which the overheads associated with ... View full abstract»

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  • Software Self-Testing of a Symmetric Cipher with Error Detection Capability

    Publication Year: 2008 , Page(s): 79 - 84
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (319 KB) |  | HTML iconHTML  

    Cryptographic devices are recently implemented with different countermeasures against side channel attacks and fault analysis. Moreover, some usual testing techniques, such as scan chains, are not allowed or restricted for security requirements. In this paper, we analyze the impact that error detecting schemes have on the testability of an implementation of the advanced encryption standard, in par... View full abstract»

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