2008 IEEE International Workshop on Hardware-Oriented Security and Trust

9-9 June 2008

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  • 2008 IEEE international workshop on hardware-oriented security and trust (HOST)

    Publication Year: 2008, Page(s): c1
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  • 2008 IEEE international workshop on hardware-oriented security and trust (HOST)

    Publication Year: 2008, Page(s): i
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  • [Copyright notice]

    Publication Year: 2008, Page(s): ii
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  • Table of contents

    Publication Year: 2008, Page(s):iii - iv
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  • Keynote address

    Publication Year: 2008, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (10 KB)

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Session 1 Hardware Trojans

    Publication Year: 2008, Page(s): 2
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  • Sensitivity analysis to hardware Trojans using power supply transient signals

    Publication Year: 2008, Page(s):3 - 7
    Cited by:  Papers (60)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB) | HTML iconHTML

    Trust in reference to integrated circuits addresses the concern that the design and/or fabrication of the IC may be purposely altered by an adversary. The insertion of a hardware Trojan involves a deliberate and malicious change to an IC that adds or removes functionality or reduces its reliability. Trojans are designed to disable and/or destroy the IC at some future time or they may serve to leak... View full abstract»

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  • At-speed delay characterization for IC authentication and Trojan Horse detection

    Publication Year: 2008, Page(s):8 - 14
    Cited by:  Papers (46)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1269 KB) | HTML iconHTML

    New attacker scenarios involving integrated circuits (ICs) are emerging that pose a tremendous threat to national security. Concerns about overseas fabrication facilities and the protection of deployed ICs have given rise to methods for IC authentication (ensuring that an IC being used in a system has not been altered, replaced, or spoofed) and hardware Trojan Horse (HTH) detection (ensuring that ... View full abstract»

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  • Detecting malicious inclusions in secure hardware: Challenges and solutions

    Publication Year: 2008, Page(s):15 - 19
    Cited by:  Papers (54)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (86 KB) | HTML iconHTML

    This paper addresses a new threat to the security of integrated circuits (ICs) used in safety critical, security and military systems. The migration of IC fabrication to low-cost foundries has made ICs vulnerable to malicious alterations, that could, under specific conditions, result in functional changes and/or catastrophic failure of the system in which they are embedded. We refer to such malici... View full abstract»

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  • Session 2 Side-channel attacks and countermeasures

    Publication Year: 2008, Page(s): 20
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  • Slicing up a perfect hardware masking scheme

    Publication Year: 2008, Page(s):21 - 25
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1000 KB) | HTML iconHTML

    Masking is a side-channel countermeasure that randomizes side-channel leakage, such as the power dissipation of a circuit. Masking is only effective on the condition that the internal random mask remains a secret. Previous research has illustrated how a successful estimation of the mask bit in circuit-level masking leads to successful side-channel attacks. In this paper, we extend this concept to ... View full abstract»

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  • Place-and-route impact on the security of DPL designs in FPGAs

    Publication Year: 2008, Page(s):26 - 32
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (225 KB) | HTML iconHTML

    Straightforward implementations of cryptographic algorithms are known to be vulnerable to attacks aimed not at the mathematical structure of the cipher but rather at the weak points of the electronic devices which implement it. These attacks, known as side-channel attacks, have proved to be very powerful in retrieving secret keys from any kind of unprotected electronic device. Amongst the various ... View full abstract»

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  • Extended abstract: A high-performance, low-overhead, power-analysis-resistant, single-rail logic style

    Publication Year: 2008, Page(s):33 - 36
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (721 KB) | HTML iconHTML

    Differential power analysis (DPA) has been shown to be an effective attack on cryptographic systems capable of revealing secret data by measuring power consumption. DPA-resistant circuits currently incur severe penalties in terms of performance, area, and power - as much as 4times in each. Additionally, most are dual-rail logic families, which can require careful attention to wire routing to ensur... View full abstract»

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  • Session 3 Invited presentation

    Publication Year: 2008, Page(s): 37
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  • The role of platform integrity in trustworthy systems

    Publication Year: 2008, Page(s): 38
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (23 KB)

    Summary form only given. This presentation discusses the role of platform integrity in platform security trustworthiness while reviewing a few basic tenants for hardware requirements to enable and support successful applications. Users demand that applications and platforms strike a delicate balance between hardware and software utility. Platforms, and their associated applications, that are too d... View full abstract»

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  • Session 4 Hardware Trojans

    Publication Year: 2008, Page(s): 39
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  • A region based approach for the identification of hardware Trojans

    Publication Year: 2008, Page(s):40 - 47
    Cited by:  Papers (76)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (563 KB) | HTML iconHTML

    Outsourcing of SoC fabrication units has created the potential threat of design tampering using hardware Trojans. Methods based on side-channel analysis exist to differentiate such maligned ICs from the genuine ones but process variation in the foundries limit the effectiveness of such approaches. In this work, we propose a circuit partition based approach to detect and locate the embedded Trojan.... View full abstract»

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  • On-demand transparency for improving hardware Trojan detectability

    Publication Year: 2008, Page(s):48 - 50
    Cited by:  Papers (31)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (351 KB) | HTML iconHTML

    Malevolent Trojan circuits inserted by layout modifications in an IC at untrustworthy fabrication facilities are difficult to detect by traditional post-manufacturing testing. In this paper, we develop a novel low-overhead design methodology that facilitates the detection of inserted Trojan hardware in an IC through logic testing. As a byproduct, it also increases the security of the design by des... View full abstract»

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  • Hardware Trojan detection using path delay fingerprint

    Publication Year: 2008, Page(s):51 - 57
    Cited by:  Papers (90)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (303 KB) | HTML iconHTML

    Trusted IC design is a recently emerged topic since fabrication factories are moving worldwide in order to reduce cost. In order to get a low-cost but effective hardware trojan detection method to complement traditional testing methods, a new behavior-oriented category method is proposed to divide trojans into two categories: explicit payload trojan and implicit payload trojan. This categorization... View full abstract»

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  • Session 5 IP piracy protection, CAD tool security and PUFs

    Publication Year: 2008, Page(s): 58
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  • Verifying the authenticity of chip designs with the DesignTag system

    Publication Year: 2008, Page(s):59 - 64
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1242 KB) | HTML iconHTML

    This paper introduces DesignTag - a novel, patented, dasiasecurity tagpsila technology which can be used to verify the authenticity of semiconductor devices. The tag takes the form of a small digital circuit which is added to the chip design and communicates through the package with an external sensor. Falsely marked dasiaghostpsila chips are present in the supply chain and cause economic damage t... View full abstract»

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  • Extended abstract: Circuit CAD tools as a security threat

    Publication Year: 2008, Page(s):65 - 66
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (166 KB) | HTML iconHTML

    The demand for trusted and tamper-resistant computing platforms has placed security at the leading edge of research and industrial practice. Reported hardware-security breaches have already led to loss of confidential information, identity theft, intercepted cellular communications, and IP burglary. Our work demonstrates that ICs can be easily compromised by tampering with CAD tools or scripts tha... View full abstract»

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  • Extended abstract: The butterfly PUF protecting IP on every FPGA

    Publication Year: 2008, Page(s):67 - 70
    Cited by:  Papers (139)  |  Patents (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (302 KB) | HTML iconHTML

    IP protection of hardware designs is the most important requirement for many FPGA IP vendors. To this end, various solutions have been proposed by FPGA manufacturers based on the idea of bitstream encryption. An alternative solution was advocated in (E. Simpson and P. Schaumont, 2006). Simpson and Schaumont proposed a new approach based on physical unclonable functions (PUFs) for IP protection on ... View full abstract»

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  • Session 6 Cryptography and securing hardware

    Publication Year: 2008, Page(s): 71
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  • Extended abstract: Unified digit-serial multiplier/inverter in finite field GF(2m)

    Publication Year: 2008, Page(s):72 - 75
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (286 KB) | HTML iconHTML

    Modular multiplication and inversion are the essential operations in both elliptic curve cryptosystems (ECC) and hyperelliptic curve cryptosystems (HECC). In this paper, we describe a unified digit-serial multiplier/inverter in GF(2m). The inverter is based on a modified extended Euclidean algorithm (EEA). When choosing digit size to be w, this multiplier/inverter finishes one inversion... View full abstract»

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