25-29 May 2008

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Displaying Results 1 - 25 of 43
  • [Cover art]

    Publication Year: 2008, Page(s): C1
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  • [Title page i]

    Publication Year: 2008, Page(s): i
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  • [Title page iii]

    Publication Year: 2008, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2008, Page(s): iv
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  • Table of contents

    Publication Year: 2008, Page(s):v - vii
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  • Foreword

    Publication Year: 2008, Page(s): viii
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  • Organizing Committee

    Publication Year: 2008, Page(s):ix - xi
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  • Steering Committee

    Publication Year: 2008, Page(s): xii
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  • Program Committee

    Publication Year: 2008, Page(s): xiii
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  • ETS 2007 Paper Award

    Publication Year: 2008, Page(s): xiv
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  • Test Technology Technical Council

    Publication Year: 2008, Page(s):xv - xvii
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  • The Role of Test in Circuits Built with Unreliable Components

    Publication Year: 2008, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (66 KB)

    The talk will reconsider the role of the test in new emerging device circuits for CMOS Terascale and further technologies where a high level of redundancy will be present. As far as we are getting close to ultimate CMOS and ulterior new emerging nano-devices technologies the indication made by J. von Neumann in 1950 that errors had to be viewed not as an extraneous accident but as an essential par... View full abstract»

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  • The Future Is Low Power and Test

    Publication Year: 2008, Page(s): 4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (74 KB)

    Summary form only given. Dr. Gordon E. Moore's Law - integration's capacity doubles every two years - is under server pressure. Leakage power is the major factor in the challenge to keep Moore's Law alive and well. As process technologies continue to shrink, and feature demands continue to increase, more and more capabilities are being pushed into smaller and smaller packages. But are we finally r... View full abstract»

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  • Safe Fault Collapsing Based on Dominance Relations

    Publication Year: 2008, Page(s):7 - 12
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB) | HTML iconHTML

    For fault models with large numbers of faults, such as bridging faults, fault collapsing based on dominance relations can be effective in reducing the test generation time by reducing the number of target faults. When dominance relations are used for fault collapsing, a fault fj is excluded from the set of target faults F if it dominates a fault fi in F. However, if fi View full abstract»

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  • A Reliable Architecture for the Advanced Encryption Standard

    Publication Year: 2008, Page(s):13 - 18
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (733 KB) | HTML iconHTML

    In this paper we propose an on-line self-test architecture for hardware implementations of advanced encryption standard (AES). The solution assumes a parallel architecture and exploits the inherent spatial replications of this implementation. We show that our solution is very effective for on-line fault detection while keeping the area overhead very low. Moreover, it does not weak the device with ... View full abstract»

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  • Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism

    Publication Year: 2008, Page(s):21 - 26
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (411 KB) | HTML iconHTML

    Test data travels through a System-on-Chip (SOC) from the chip pins to the module-under-test and vice versa via a Test Access Mechanism (TAM). Conventionally, a TAM is implemented with dedicated wires. However, also existing functional interconnect, such as a bus or Network-on-Chip (NOC), can be reused as TAM. This will reduce the overall design effort and the silicon area. For a given module, its... View full abstract»

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  • Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design

    Publication Year: 2008, Page(s):27 - 32
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (356 KB) | HTML iconHTML

    This article describes an analog test bus infrastructure as a straightforward approach to grant the accessibility to embedded RF or Analog modules in core-based design. This DfT method increases the testability and provides debug/diagnosis facilities. The standardized analog test bus architecture is suited for an automated test development flow. In addition, the entire infrastructure is to a large... View full abstract»

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  • Confidence Estimation in Non-RF to RF Correlation-Based Specification Test Compaction

    Publication Year: 2008, Page(s):35 - 40
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7446 KB) | HTML iconHTML

    Several existing methodologies have leveraged the correlation between the non-RF and the RF performances of a circuit in order to predict the latter from the former and, thus, reduce test cost. While this form of specification test compaction eliminates the need for expensive RF measurements, it also comes at the cost of reduced test accuracy, since the retained non-RF measurements and pertinent c... View full abstract»

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  • Built-in Test of Frequency Modulated RF Transmitters Using Embedded Low-Pass Filters

    Publication Year: 2008, Page(s):41 - 46
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (739 KB) | HTML iconHTML

    Frequency modulation is used in many important communication and wireless applications. A key defining characteristic of frequency modulated systems is the constant amplitude of the transmitted signal making it impossible to use envelope-based built-in test (BIT) techniques. In this paper, an efficient BIT technique for such transmitters using lowpass filters is proposed. The proposed BIT techniqu... View full abstract»

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  • Using Temperature as Observable of the Frequency Response of RF CMOS Amplifiers

    Publication Year: 2008, Page(s):47 - 52
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1045 KB) | HTML iconHTML

    The power dissipated by the devices of an integrated circuit can be considered a signature of the circuit's performance. Without disturbing the circuit operation, this power consumption can be monitored by temperature measurements on the silicon surface. In this paper, the frequency response of a RF LNA is observed by measuring spectral components of the sensed temperature. Results prove that temp... View full abstract»

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  • A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

    Publication Year: 2008, Page(s):55 - 60
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (451 KB) | HTML iconHTML

    Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and pract... View full abstract»

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  • Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation

    Publication Year: 2008, Page(s):61 - 68
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB) | HTML iconHTML

    The paper proposes a novel method for PSL language assertions simulation-based checking. The method uses a system representation model called High-level decision diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. The presented approach proposes a temporal extension for the existing HLDD model aimed at supporting tempo... View full abstract»

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  • On Bypassing Blocking Bugs during Post-Silicon Validation

    Publication Year: 2008, Page(s):69 - 74
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB) | HTML iconHTML

    Design errors (or bugs) inadvertently escape the pre- silicon verification process. Before committing to a re-spin, it is expected that the escaped bugs have been identified during post-silicon validation. This is however hindered by the presence of blocking bugs in one erroneous module that inhibit the search for bugs in other parts of the chip that process data received from the erroneous module... View full abstract»

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  • Applying March Tests to K-Way Set-Associative Cache Memories

    Publication Year: 2008, Page(s):77 - 83
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (289 KB) | HTML iconHTML

    Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system test. The application of test algorithms for SRAM memories to cache memories thus requires opportune transformations. In this paper we present a procedure to adapt traditional march tests to testing the data and the directory array of k-way set-associative cache memories ... View full abstract»

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  • Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories

    Publication Year: 2008, Page(s):84 - 90
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB) | HTML iconHTML

    The framework of this article lies in the dynamic management of the reliability in NOR embedded Flash memories (eFlash). The main objective is to build a new reliability management scheme and to predict its efficiency to improve the eFlash reliability using error correction code and redundancy. The originality of the proposed approach relies on the use of a dedicated error correcting code well sui... View full abstract»

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