2008 45th ACM/IEEE Design Automation Conference

8-13 June 2008

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  • Table of contents

    Publication Year: 2008, Page(s):I - XXIII
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  • General chair’s message

    Publication Year: 2008, Page(s): i
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  • Proceedings of the 45th design automation conference

    Publication Year: 2008, Page(s): ii
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  • Executive Committee

    Publication Year: 2008, Page(s):iii - x
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  • EDA for digital, programmable, multi-radios

    Publication Year: 2008, Page(s): xi
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (124 KB)

    New technology and innovative usage models are driving the industry towards the ubiquitous use of wireless communications. The result is an end-to-end re-examination of radio architecture from the front end module to the MAC and the expected shift from largely analog to nearly pure digital radio design. Even RF power amplifiers will be digital, rather than analog in nature. Most importantly, radio... View full abstract»

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  • Challenges on design complexities for advanced wireless silicon systems

    Publication Year: 2008, Page(s): xii
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (120 KB)

    The global wireless landscape continues to change as demand for 3G technology accelerates. Qualcomm is meeting the challenge with its highly integrated SoC solutions that enable customers worldwide to bring more advanced consumer devices to market faster. Relationships and tight collaboration continue to play an integral role in product development, as it becomes more crucial than ever for partner... View full abstract»

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  • Idea to implementation: A different perspective on system design

    Publication Year: 2008, Page(s): xiii
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (121 KB)

    Today’s electronic devices are multi-faceted, software-intensive systems that interact with the real world. These interactions create a new kind of complexity that increases pressure on engineering teams to deliver the right product under shrinking schedules. These multi-disciplinary teams are inhibited by gaps between the different tools and workflows they must use for system concept devel... View full abstract»

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  • Marie R. Pistilli Women in EDA Achievement Award

    Publication Year: 2008, Page(s):xiv - xvii
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  • Reviewers

    Publication Year: 2008, Page(s):xviii - xxi
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  • Call for papers

    Publication Year: 2008, Page(s):xxii - xxiv
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  • Flow engineering for physical implementation: Theory and practice

    Publication Year: 2008, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (474 KB) | HTML iconHTML

    Two consultants, each with over twenty years of experience designing integrated circuits at a variety of companies large and small, are fed up with the imperfect flows typically used by their clients. Drawing on a career's worth of mistakes knowledge, they present a set of coherent engineering principles for building a better flow infrastructure. View full abstract»

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  • Sparse matrix computations on manycore GPU’s

    Publication Year: 2008, Page(s):2 - 6
    Cited by:  Papers (2)  |  Patents (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (849 KB) | HTML iconHTML

    Modern microprocessors are becoming increasingly parallel devices, and GPUs are at the leading edge of this trend. Designing parallel algorithms for manycore chips like the GPU can present interesting challenges, particularly for computations on sparse data structures. One particularly common example is the collection of sparse matrix solvers and combinatorial graph algorithms that form the core o... View full abstract»

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  • Parallel programming: Can we PLEASE get it right this time?

    Publication Year: 2008, Page(s):7 - 11
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (606 KB) | HTML iconHTML

    The computer industry has a problem. As Moore's law marches on, it will be exploited to double cores, not frequencies. But all those cores, growing to 8, 16 and beyond over the next several years, are of little value without parallel software. Where will this come from? With few exceptions, only graduate students and other strange people write parallel software. Even for numerically intensive appl... View full abstract»

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  • Parallelizing CAD: A timely research agenda for EDA

    Publication Year: 2008, Page(s):12 - 17
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (389 KB) | HTML iconHTML

    The relative decline of single-threaded processor performance, coupled with the ongoing shift towards on chip parallelism requires that CAD applications run efficiently on parallel microprocessors. We believe that an ad hoc approach to parallelizing CAD applications will not lead to satisfactory results: neither in terms of return on engineering investment nor in terms of the computational efficie... View full abstract»

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  • Functionally linear decomposition and synthesis of logic circuits for FPGAs

    Publication Year: 2008, Page(s):18 - 23
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (282 KB) | HTML iconHTML

    This paper presents a novel logic synthesis method to reduce the area of XOR-based logic functions. The idea behind the synthesis method is to exploit linear dependency between logic sub- functions to create an implementation based on an XOR relationship with a lower area overhead. Experiments conducted on a set of 99 MCNC benchmark (25 XOR based, 74 non-XOR) circuits show that this approach provi... View full abstract»

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  • FPGA area reduction by multi-output function based sequential resynthesis

    Publication Year: 2008, Page(s):24 - 29
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (445 KB) | HTML iconHTML

    We propose a new resynthesis algorithm for FPGA area reduction. In contrast to existing resynthesis techniques, which consider only single-output Boolean functions and the combinational portion of a circuit, we consider multi-output functions and retiming, and develop effective algorithms that incorporate recent improvements to SAT-based Boolean matching. Our experimental results show that with th... View full abstract»

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  • A generalized network flow based algorithm for power-aware FPGA memory mapping

    Publication Year: 2008, Page(s):30 - 33
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (463 KB) | HTML iconHTML

    In this paper, we present a generalized network flow based algorithm for power-aware FPGA memory mapping. Our algorithm not only maps user-defined logical memories to physical embedded memory blocks under the memory resource constraint but also achieves minimum power consumption. The experimental results show that our algorithm was always able to efficiently generate optimal solutions for all test... View full abstract»

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  • Enhancing timing-driven FPGA placement for pipelined netlists

    Publication Year: 2008, Page(s):34 - 37
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (286 KB) | HTML iconHTML

    FPGA application developers often use pipelining, C-slowing and retiming to improve the performance of their designs. Unfortunately, registered netlists present a fundamentally different problem to CAD tools, potentially limiting the benefit of these techniques. In this paper we discuss some of the inherent issues pipelined netlists pose to existing timing-driven placement approaches. We then pres... View full abstract»

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  • Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variations

    Publication Year: 2008, Page(s):38 - 43
    Cited by:  Papers (1)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (440 KB) | HTML iconHTML

    The continuous technology scaling brings about high-dimensional performance variations that cannot be easily captured by the traditional response surface modeling. In this paper we propose a new statistical regression (STAR) technique that applies a novel strategy to address this high dimensionality issue. Unlike most traditional response surface modeling techniques that solve model coefficients f... View full abstract»

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  • Topology synthesis of analog circuits based on adaptively generated building blocks

    Publication Year: 2008, Page(s):44 - 49
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (444 KB) | HTML iconHTML

    This paper presents an automated analog synthesis tool for topology generation and subsequent circuit sizing. Though sizing is indispensable, the paper mainly concentrates on topology generation. A new kind of GA is developed, where a fraction of the offsprings in each generation is built from building blocks or cells obtained from previous generations. The cells are stored in a hierarchically arr... View full abstract»

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  • Analog placement based on hierarchical module clustering

    Publication Year: 2008, Page(s):50 - 55
    Cited by:  Papers (2)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (535 KB) | HTML iconHTML

    In analog layout design, it is very important to reduce the parasitic coupling effects and improve the circuit performance. Consequently, the most important device-level placement constraints are matching, symmetry, and proximity. However, many previous works deal with these constraints separately, and none of them mention how to handle different constraints simultaneously and hierarchically. In t... View full abstract»

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  • Run-time instruction set selection in a transmutable embedded processor

    Publication Year: 2008, Page(s):56 - 61
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (975 KB) | HTML iconHTML

    We are presenting a new concept of an application-specific processor that is capable of transmuting its instruction set according to non-predictive application behavior during run-time. In those scenarios, current (extensible) embedded processors are less efficient since they are not run-time adaptive. We have identified the instruction set selection to be a critical step to perform at run time an... View full abstract»

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  • Rapid application specific floating-point unit generation with bit-alignment

    Publication Year: 2008, Page(s):62 - 67
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (458 KB) | HTML iconHTML

    While ASIPs have allowed designers to create processors with custom instructions to target specific applications, floating point units are still instantiated as fixed general-purpose units, which wastes area if not fully utilized. Therefore, there is a need for custom FPUs for embedded systems. The creation of a custom FPU requires the selection of a subset of the full floating-point instruction s... View full abstract»

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  • Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency

    Publication Year: 2008, Page(s):68 - 71
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (358 KB) | HTML iconHTML

    With CMOS scaling leading to ever increasing levels of transistor integration on a chip, designers of high-performance embedded processors have ample area available to increase processor resources in order to improve performance. However, increasing resource sizes can increase power dissipation and also reduce access time, which can limit maximum achievable operating frequency. In this paper, we e... View full abstract»

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  • C-based design flow: A case study on G.729A for Voice over internet protocol (VoIP)

    Publication Year: 2008, Page(s):72 - 75
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (451 KB) | HTML iconHTML

    In this paper we present the design of a G.729a codec in a C- based design flow. The codec is used in VoIP applications for sending speech over internet protocol. We started from the standard reference C implementation and generated several customized designs using the NISCT C-to-RTL toolset. Our final designs could run at very low clock frequencies (11 MHz for the decoder and 30 MHz for the coder... View full abstract»

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