Date 1-4 June 2008
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Displaying Results 1 - 25 of 72
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Contributor Listings
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PDF (93 KB)
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Table of contents
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PDF (112 KB)
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Through-Silicon Via Technologies for Extreme Miniaturized 3D Integrated Wireless Sensor Systems (e-CUBES)
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PDF (565 KB)
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Three-Dimensional Integration Technology Using Self-Assembly Technique and Super-Chip Integration
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PDF (1054 KB)
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Extraction of the Appropriate Material Property for Realistic Modeling of Through-Silicon-Vias using μ-Raman Spectroscopy
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PDF (293 KB)
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Resistance to electromigration of purely intermetallic micro-bump interconnections for 3D-device stacking
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PDF (2426 KB)
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Development and optimization of porous pSiCOH interconnect dielectrics for 45 nm and beyond
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PDF (150 KB)
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A Self-Aligned Air Gap Interconnect Process
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PDF (3041 KB)
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Production Worthy 3D Interconnect Technology
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PDF (370 KB)
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3D Die-to-wafer Cu/Sn Microconnects Formed Simultaneously with an Adhesive Dielectric Bond Using Thermal Compression Bonding
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PDF (421 KB)
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Voltage Ramp and Time-Dependent Dielectric Breakdown in Ultra-Narrow Cu/SiO
2 Interconnects
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PDF (461 KB)
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Key factors to sustain the extension of a MHM-based integration scheme to medium and high porosity PECVD low-k materials
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PDF (423 KB)
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Analytical Study of leakage characteristics change during multilevel interconnect process using porogen-type porous SiOC (k=2.4)/Cu system
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PDF (443 KB)
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Copper direct bonding for 3D integration
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PDF (228 KB)
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Structure-Designable Formation-Method of Super Low-k SiOC Film (k=2.2) by Neutral-Beam-Enhanced-CVD
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PDF (291 KB)
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Micro Beam IR Characterization of Narrow Width (-100 nm) Low-k Spaces Between Cu Lines Correlated with Valence EELS Evaluation
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PDF (851 KB)


