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38th International Symposium on Multiple Valued Logic (ismvl 2008)

Date 22-24 May 2008

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Displaying Results 1 - 25 of 52
  • [Front cover]

    Publication Year: 2008, Page(s): C1
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  • [Title page i]

    Publication Year: 2008, Page(s): i
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  • [Title page iii]

    Publication Year: 2008, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2008, Page(s): iv
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  • Table of contents

    Publication Year: 2008, Page(s):v - viii
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  • Message from the Symposium Chair

    Publication Year: 2008, Page(s): ix
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  • Message from the Program Chair

    Publication Year: 2008, Page(s): x
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  • Conference Committees

    Publication Year: 2008, Page(s):xi - xii
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  • EDA to the Rescue of the Silicon Roadmap

    Publication Year: 2008, Page(s): 1
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (69 KB) | HTML iconHTML

    Summary form only given. Since the invention of the transistor, new technology nodes have been added approximately every two years. This march of progress has yielded smaller transistors that run about 40% faster with each geometry scaling, fulfilling the promise and industry-defining mantra of "smaller, faster, cheaper!". Now, in the realm of 65- and 45-nanometer design and manufacturing, the ind... View full abstract»

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  • A Mature Methodology for Implementing Multi-Valued Logic in Silicon

    Publication Year: 2008, Page(s):2 - 7
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (186 KB) | HTML iconHTML

    This paper gives an overview of methods proposed for implementing multi-valued logic in CMOS and then describes Intrinsity's patented Fast14reg Technology as a mature methodology for silicon implementation of multi-valued logic. To the authors' knowledge, no previous method of implementing multi-valued logic has been demonstrated with a design of the complexity of a microprocessor core.... View full abstract»

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  • Design of High-Performance Quaternary Adders Based on Output-Generator Sharing

    Publication Year: 2008, Page(s):8 - 13
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (247 KB) | HTML iconHTML

    Simple implementations of quaternary full adders are proposed for a high-performance multi-processor which consists of many processing elements (PEs). Arbitrary quaternary functions are represented by the combination of input-value conversion and several quaternary output generations. The use of appropriate input-value conversion makes it possible to reduce the number of output generators, which i... View full abstract»

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  • Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices

    Publication Year: 2008, Page(s):14 - 19
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (472 KB) | HTML iconHTML

    A compensation method against a threshold-voltage (Vth) variation using tunneling magnetoresistive (TMR) devices, is proposed for a deep-submicron VLSI. The influence of the Vth variation in a single MOS transistor can be neglected by adjusting the source voltage of the MOS transistor. The desired circuit behavior is obtained by programming the resistance value of a TMR devic... View full abstract»

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  • Time-Domain Pre-Emphasis Techniques for Equalization of Multiple-Valued Data

    Publication Year: 2008, Page(s):20 - 25
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (765 KB) | HTML iconHTML

    This paper presents a new equalization technique based on a pulse-width modulation (PWM) pre-emphasis method which utilizes time-domain information processing to increase the data rate for a given bandwidth of VLSI interconnection. The pre-emphasis method does not change the pulse amplitude as for conventional FIR pre-emphasis, but instead exploits timing resolution. This fits well with recent CMO... View full abstract»

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  • Betweenness, Metrics and Entropies in Lattices

    Publication Year: 2008, Page(s):26 - 31
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    We investigate a class of metrics on lattices that are compatible with the partial order defined by the lattice using the ternary relation of betweenness that can be naturally defined on a metric space. The relationships between entropy-like functions and metrics defined on lattices are studied and we show the links that exists between various properties of entropies and properties of metrics. App... View full abstract»

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  • On Maximal Hyperclones on {0, 1} A New Approach

    Publication Year: 2008, Page(s):32 - 37
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (218 KB) | HTML iconHTML

    The set of clones of operations on {0,1} forms a countable lattice which was classified by Post. The cardinality of the lattice of hyperclones on {0,1} was proved by Machida to be of the continuum. The hypercore of a clone C is zeta- closure of the set of hyperoperations whose extended operations belong to C. For every clone C which is intersection of the clone B5 and another submaximal... View full abstract»

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  • Majority and Other Polynomials in Minimal Clones

    Publication Year: 2008, Page(s):38 - 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB) | HTML iconHTML

    A minimal clone is an atom of the lattice of clones. A minimal function is, briefly saying, a function which generates a minimal clone. For a prime power k we consider the base set with k elements as a finite field GF(k). We present binary idempotent minimal polynomials and ternary majority minimal polynomials over GF(3) and generalize them to minimal polynomials over GF(k) for any prime power k g... View full abstract»

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  • Comparative Study by Solving the Test Compaction Problem

    Publication Year: 2008, Page(s):44 - 49
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (330 KB) | HTML iconHTML

    Beside issues like the low power dissipation and the increase of defect coverage, test compaction is an important requirement regarding large scale integration (LSI) testing. The overall cost of a VLSI circuit's testing depends on the length of its test sequence; therefore the reduction of this sequence, keeping the coverage, will lead to a reduction of used resources in the testing process. In th... View full abstract»

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  • Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators

    Publication Year: 2008, Page(s):50 - 56
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB) | HTML iconHTML

    This paper proposes a method to represent two-variable elementary functions using edge-valued multi-valued decision diagrams (EVMDDs), and presents a design method and an architecture for function generators using EVMDDs. To show the compactness of EVMDDs, this paper introduces a new class of integer-valued functions, l-restricted Mp-monotone increasing functions, and derives an upper bound on the... View full abstract»

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  • On the Complexity of Classification Functions

    Publication Year: 2008, Page(s):57 - 63
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB) | HTML iconHTML

    A classification function is a multiple-valued input function specified by a set of rules, where each rule is a conjunction of range functions. The function is useful for packet classification for internet, network intrusion detection system, etc. This paper considers the complexity of range functions and classification functions represented by sum-of-products expressions of binary variables. It g... View full abstract»

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  • MDD with Added Null-Value and All-Value Edges

    Publication Year: 2008, Page(s):64 - 69
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (194 KB) | HTML iconHTML

    This paper presents an MDD that has additional null-value and all-value edges. The MDD is based on a multi-valued algebra that augments multi-valued variables to allow a null- output value. A null-output value is a value that cannot be computed but represents the lack of any valid value for a given input combination (akin to an output don't care, but its value cannot be changed). A side effect of ... View full abstract»

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  • High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit

    Publication Year: 2008, Page(s):70 - 75
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (542 KB) | HTML iconHTML

    A high-speed timing verification scheme using delay tables is proposed for a large-scaled multiple-valued current- mode (MVCM) circuit. A multi-level input-signal transition in the MVCM circuit is decomposed of binary signal transitions whose behaviors are represented using delay tables as higher abstracted description than transistor-level one. This high-level abstraction makes it possible to gre... View full abstract»

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  • Permutations under Spectral Transforms

    Publication Year: 2008, Page(s):76 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (229 KB) | HTML iconHTML

    The paper studies the conditions under which permutations on the truth vector of a multiple-valued function are preserved under a spectral transform. Both the cases of the Vilenkin-Chrestenson and of the Generalized Reed Muller transforms are discussed. One condition to preserve a permutation is that the corresponding permutation matrix is self-similar under the transform matrix. View full abstract»

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  • On Fixed Points and Cycles in the Reed Muller Domain

    Publication Year: 2008, Page(s):82 - 87
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB) | HTML iconHTML

    This paper studies cycles that appear by repeatedly applying the RM transform to a p-valued function. It is shown that there are nontrivial fixed points, which correspond to eigenvectors of the transform and a simple method is proposed to determine the maximum period of n-place functions for a given p. The concept of spectral diversity is introduced, which may be applied to ch... View full abstract»

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  • A Galois Field Approach to Modelling Gene Expression Regulation

    Publication Year: 2008, Page(s):88 - 93
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (257 KB) | HTML iconHTML

    Gene expression is the process by which the cell transforms the information in the DNA to functions, often carried out by proteins. Which genes will be expressed, depends on many factors some internal to the cell and others from the environment around it. This can be considered as a logic function prescribing gene expression in response to the different conditions. Apart from continuous models, th... View full abstract»

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  • On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults

    Publication Year: 2008, Page(s):94 - 99
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (707 KB) | HTML iconHTML

    Automatic Test Pattern Generation (ATPG) is an important task to ensure that a chip functions correctly. For high speed chips, testing for dynamic fault models such as the path delay fault model becomes more and more important. While classical algorithms for ATPG reach their limit, the significance of algorithms to solve the Boolean Satisfiability (SAT) problem grows due to recent developments of ... View full abstract»

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