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Memory Technology, Design and Testing, 2007. MTDT 2007. IEEE International Workshop on

Date 3-5 Dec. 2007

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Displaying Results 1 - 25 of 26
  • Message from the General Chairs

    Publication Year: 2007 , Page(s): ii - iv
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  • System-in-Package design/testing in memory package

    Publication Year: 2007 , Page(s): 1
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    Summary form only given. Miniaturization, electric performance and cost have drove the package thinner and thinner. System-in-package (SIP) and system-on-chip (SOC) are two competitive solutions. SIP is becoming the mainstream in assembly, which is able to short the design cycle time and speed up the new product introduction, especially in the mobile phone, hand held product and memory products. Stack dice, PoP (package-on-package) is mature and has been widely and growing up the market share. Embedded dice/substrate, fan-out-WLCSP, and TSV (through silicon via) are coming soon. Many new technology, especially for memory has been developed, they will be discussed during the sections. View full abstract»

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  • Future challenges and opportunities of the memory industry

    Publication Year: 2007 , Page(s): 2 - 3
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    The still ongoing digital revolution of the 21st century has changed the daily life of a great number of people. The explosive growth of the semiconductor industry, which reached about 16% per year in the past, was based on two pillars; the incessant demand for information-related goods and the advance in process & device integration technology, which satisfied the need for enhancing system performance and reducing production costs. View full abstract»

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  • High-performance SRAM in nanoscale CMOS: Design challenges and techniques

    Publication Year: 2007 , Page(s): 4 - 12
    Cited by:  Papers (11)
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    This paper reviews the design challenges and techniques of high-performance SRAM in the "End of Scaling" nanoscale CMOS technologies. The impacts of technology scaling, such as signal loss due to leakage, degradation of noise margin due to VT scatter caused by process variations and random dopant fluctuation, and long term reliability degradation such as NBTI, are addressed. Design directions and leakage/variation/degradation tolerant SRAM circuit techniques to mitigate various performance and reliability constraints in conventional planar CMOS technology are discussed. Examples are given and merits discussed for cell isolation and strength preservation, thin cell layout, bit-line and word-line leakage mitigation, migration to large signal read-out, undamped bit-line, dual-supply, dynamic Read/Write supply, floating power-line, header/footer power-gating structures, Read- and Write-assist circuits, leakage/variation detection and compensation techniques, word-line and bit-line pulsing schemes, gate leakage tolerant design, and NBTI tolerant design. Alternative cell structures, such as asymmetrical SRAM, 7T, and 8T SRAMs, which decouple the cell storage node from the Read-disturb and half-select disturb to improve the SNM are discussed. Finally, some design issues and opportunities in emerging technologies such as FD/SOI and multi-gate FinFET are illustrated. View full abstract»

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  • Value creation and technological convergence by evolution of embedded non-volatile memory

    Publication Year: 2007 , Page(s): 13 - 14
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    Flash-MCU, micro-controller with embedded flash memory storage (eFlash), has seen a tremendous up-surge in real-time control application markets, with assumed 20% CAGR. The programmable code storage provided by eFlash contributes to production cost reduction and real-time adaptive control applications, realizing a value innovation with remarkable cost/value advantage. The diversified advanced eFlash technology for converging flash-MCU products challenges new market drivers like automotive and smart-IC cards. Current status and future directions of flash-MCU in view of how on-chip programmability function evolution contributes to innovate MCU/SOC applications are overviewed. The 3rd generation MCU products as realized by NV-RAM concepts will drive a convergence into unified technology by value creation opportunities provided. View full abstract»

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  • Variability, margins, and unpredictability: Dealing with uncertainty in SRAM design

    Publication Year: 2007 , Page(s): 15
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    As process technology continues to advance, SRAM design is becoming increasingly critical. Not only does memory occupy a large portion of the design, but memory structures are increasingly susceptible to yield and variability issues than. Classical design validation and margining methods must be extended to cope with new challenges, including low power operation, accurate modeling, blurring lines between defects and variability, and limits of classical scaling. This talk addresses these issues and discusses new approaches they require. View full abstract»

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  • Scaling trend of the Flash memory for file storage

    Publication Year: 2007 , Page(s): 16
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    This paper describes the review of flash memory. First, the fundamental device and design characteristics of flash memory are shown. Next, recent developments of flash memory are reviewed. The flash memory cell structure can be classified into two types; floating gate type and charge trap type. Both current technologies are introduced. Third, road map and scaling issues of flash memory are summarized. View full abstract»

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  • Future trend of flash memories

    Publication Year: 2007 , Page(s): 17 - 18
    Cited by:  Papers (2)
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    Summary form only given. Flash memories have provided reliable solid-state storage solutions for over twenty years. In the last few years we have seen an explosive growth of NAND flash, fueled by digital camera, USB, MP3, iPhone and numerous new mobile applications. However, this phenomenal boom is silently threatened by scaling limitations intrinsically built into the flash devices. Old challenges such as scaling the charge tunneling oxide have remained unconquered (and now proven unconquerable) for nearly a decade, and new challenges such as floating gate cross talk become more serious with scaling. Will flash technology be simply a brief flash in the history of semiconductor? In this talk we will start with the flash memory technology and market trend. We will then discuss the scaling issues for NOR and NAND floating gate devices, and their fundamental limitations. Potential solutions, including both new devices and architecture and completely new types of non-volatile memory will then be discussed. Recent progresses in new NAND and NOR flash memory solutions or substitutes such as TANOS, BE-SONOS, 3D stacking and phase change memory will be examined in considerable details. View full abstract»

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  • Embedded SRAM trend in nano-scale CMOS

    Publication Year: 2007 , Page(s): 19 - 22
    Cited by:  Papers (6)
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    This paper describes an SRAM scaling trend in terms of bit-cell size and operating voltage (Vdd) in a nano-scale process generation. The key design solutions to extend a 6T SRAM lifetime are reviewed and discussed including a possible bit cell scaling trend comparing with an 8T SRAM as one of the successors. Each dependency of 3 key margins of write margin (WRM), static noise margin (SNM), and cell current (Icell) on the scaling ratio of Vdd and MOSFET channel feature size has been shown to clarify the real issues in the scaling. The bit cell area scaling trends of 6T and 8T SRAMs are predicted. It has been shown that the area of 6T will be getting closer to that of 8T at 32 nm and should cross over around 22 nm. View full abstract»

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  • Process variability considerations in the design of an eSRAM

    Publication Year: 2007 , Page(s): 23 - 26
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    Process variation constitutes a serious hindrance to the performance of SRAMs, since memories require bigger design margins for their proper operations. In this paper, we propose a new dummy bit line driver structure and its statistical sizing method to reduce the sensitivity of the memory with respect to process variations, while improving the read timing margin. The dummy bit line driver is an essential component in a self-timed memory during a read operation. It triggers the sense amplifier at the appropriate time when bit line is discharged. We considered a 256 kb SRAM in a 90 nm technology node. View full abstract»

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  • A Controllable low-power dual-port embedded SRAM for DSP processor

    Publication Year: 2007 , Page(s): 27 - 30
    Cited by:  Papers (1)
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    In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condition of the memory module can be arbitrarily adjusted by using software programming. The integration of low-power dual-port 8KB SRAM and the multi-threaded DSP engine is implemented in TSMC 130 nm CMOS technology. By using these techniques, the overall access power reduction of the DSP core is around 15.30%-16.84%. View full abstract»

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  • How far can we go in wireless testing of memory chips and wafers?

    Publication Year: 2007 , Page(s): 31 - 32
    Cited by:  Papers (2)
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    Summary form only given. Test cost has become a significant portion of the cost structure in advanced semiconductor memory products. To address this issue at both the wafer and packaged-chip levels, we propose HOY - a novel wireless test system with enhanced embedded test features. In this talk we will briefly outline Project HOY and the test systems and applications it defines, with focus on memory chips and wafers. Our vision is that high-end memory IC testing can go wireless in a few years. Therefore, HOY is intended as a next-generation memory test system, with wireless communication and enhanced embedded test features, such as built-in self test (BIST) and built-in self-repair (BISR). View full abstract»

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  • RAMSES-D: DRAM fault simulator supporting weighted coupling fault

    Publication Year: 2007 , Page(s): 33 - 38
    Cited by:  Papers (1)
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    Memory fault simulator is an important tool for memory test sequence optimization. Traditionally, we use fault count to calculate fault coverage. However, it cannot represent accurately the real coupling fault distribution. In this paper, we adopt the concept of weighted coupling fault targeting DRAM. We propose a weighted fault coverage function with assigning weight parameters to coupling faults. With the weighted function, we can use physical information to calculate coupling fault coverage. Experimental result shows that the weight of intra-word coupling fault can be 10% to 14%; while the original fault count method cannot distinguish the degree of importance between different memory configurations. View full abstract»

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  • Resilient SRAM design using BIST-assisted Timing Tracking

    Publication Year: 2007 , Page(s): 39 - 41
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    In this paper, an SRAM design using BIST-assisted timing-tracking (BITT) scheme to improve parametric yield by 76.7% as compared with the traditional timing-tracking method has been presented. This scheme combines reconfigurable delay line, which is tunable by memory BIST, with dummy bitline timing tracking. Consequently, the timing skew due to cell current fluctuations and imbalanced sense amplifiers can both be taken into account so as to provide more flexible timing control for future nanometer technologies. View full abstract»

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  • Power-gating current test for static RAM in nanotechnologies

    Publication Year: 2007 , Page(s): 42 - 45
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    Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is also developed for fast test generation. Analyses on transistor level bridging faults prove the test effectiveness. The proposed scheme can explore the current resolution improvement up to the generic switch intensity ratio of the double threshold-voltage CMOS technology. From simulations in a 0.13 mum technology, the current resolution can be improved by about 40 dB, i.e., 100 times. Once current test can be renascent for embedded memory, the test time can be dramatically reduced. View full abstract»

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  • An automatic design for flash memory testing

    Publication Year: 2007 , Page(s): 46 - 49
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    Due to the easy implementation and high fault coverage, the march-like algorithms have been used for the flash memory testing. However, the testing complexity of the flash memory testing is mainly dominated by the memory address spaces. Many tremendous human efforts are required to design a built-in self-test test pattern generator for a large capacity of flash memory. To save the design overhead, an automatic design for any size of flash memory testing has been proposed in this paper. By using the Microsoft Visual Basic (VB) programming tool, a graphical user interface (GUI) has been designed for the user to apply the specification of flash memory. Then the test pattern generator of the embedded march-like algorithms for testing the flash memory has been designed automatically and converted to the hardware description language (HDL) file. Under the control of the VB, without any manual labor, the HDL file can be compiled and simulated by the Altera FPGA tool - Quartus II and converted to the specific files for applying the Data Generator Instruments to generate the test signals. View full abstract»

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  • Next-generation non-volatile memory

    Publication Year: 2007 , Page(s): 50
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    Recently, Next-generation non-volatile memories continue to receive great attention due to its scalability, rapid read and write performance, simple structure, and easy incorporation with CMOS process. There are many candidates for ideal non-volatile memory, such as Magnetro-resistive RAM (MRAM), Phase change RAM (PCRAM), and Resistive RAM (RRAM). This talk will discuss the strengths and weaknesses of different emerging non-volatile memory technologies and introduce the current status of the new non-volatile memory research program at ITRI. View full abstract»

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  • The polarity dependence of ONO thickness for wrapped-select-gate (WSG) SONOS memory

    Publication Year: 2007 , Page(s): 51 - 54
    Cited by:  Papers (1)
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    2-bits/cell operation characteristics of WSG-SONOS memory has been fully studied in different ONO thickness. The 2-bits/cell characteristics of WSG-SONOS memory will be determined by tunneling oxide and total ONO thicknesses. Besides, thicker top oxide thickness will contribute to better gate disturbance performance while maintaining the same drain disturbance. We also found that the excellent endurance can be performed for the device with thinner tunneling oxide thickness. Optimized ONO thickness for WSG-SONOS memory will be demonstrated in this paper. View full abstract»

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  • A novel poly-Si nanowire TFT for nonvolatile memory applications

    Publication Year: 2007 , Page(s): 55 - 56
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    A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window. View full abstract»

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  • Improving the speed and power of compilable SRAM using dual-mode self-timed technique

    Publication Year: 2007 , Page(s): 57 - 60
    Cited by:  Papers (2)  |  Patents (1)
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    A long bitline precharge time in the write operation and a wide wordline pulse width in the read operation dominate the cycle time of large-capacity compilable SRAMs. A data-dependent bitline leakage current causes timing skew and erodes the sensing margin of conventional replica-column controlled embedded SRAM. A dual-mode self-timed (DMST) technique is proposed to generate two individual timing for the read and write operations, unlike in conventional SRAMs, in which they have the same control timing, to reduce the cycle time and power consumption of the SRAM. The RC delay on bitlines, variations in the write response time of a bitcell and data-dependent bitline leakage current are considered in the DMST. The DMST technique reduces the cycle time and the write active power consumption by 16%~30.7% and 15%~22.7%, respectively for a 65 nm 512 Kb SRAM. View full abstract»

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  • Vulnerability analysis of secure USB flash drives

    Publication Year: 2007 , Page(s): 61 - 64
    Cited by:  Papers (2)
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    USB flash drive without any security function causes the exposure of private information. So new USB flash drive supported security function was invented to compensate for the problem. In this paper, we analyze vulnerability of 6 famous secure USB flash drives, and demonstrate that password can be exposed on communication between the secure USB flash drive and PC. Also we show the vulnerability on the data recovery and the S/W bug of secure USB flash drive. View full abstract»

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  • Logic-compatible embedded NVM for RFID application

    Publication Year: 2007 , Page(s): 65 - 66
    Cited by:  Papers (1)
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    In this paper, we described the design of logic-process compatible embedded non-volatile memory (NVM) macro for the application of radio frequency identification (RFID). A prototype 1024-bits NVM test chip fabricated by 0.18 mum standard CMOS process is described and characterized. The characterization result shows write power is only 90 uW for write operation and 2 uW @0.5 MHz for read operation. The minimum VCC for read operation can be as low as 0.68 V at -40degC. Macro size of 1024-bits IP is only 0.215 mm2. View full abstract»

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  • An ALU cluster intellectual property for magnetic RAM media applications platform

    Publication Year: 2007 , Page(s): 67 - 70
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    The next generation memory, magnetic random access memory (MRAM), is a high-profile choice of embedded memory in modern applications. Features of the novel memory make it suitable for universal memory applications. Besides, as the evolution of information technology, embedded systems with media applications for portable devices are more important in modern life. In both of the perspectives mentioned above, a processing element called arithmetic logic unit (ALU) cluster intellectual property (IP) is designed and implemented to be integrated with MRAM and the platform baseboard in this work. To stack these components such as an ALU cluster, MRAM and versatile baseboard provides a development, verification and demonstration platform for the highly-expected MRAM. The proposed ALU cluster IP with advanced microcontroller bus architecture (AMBA) interface is taped out using TSMC 0.15 um technology and operates at 100 MHz. The chip area is 3.9*3.9 mm2 and gate count is 0.2 million. A 4-layer FRP printed circuit board (PCB) is designed and fabricated as the daughter card for system integration. The daughter card carries the designed chip is integrated to ARM versatile platform board and the PCB of MRAM as the system integration and application development environment. View full abstract»

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  • Author index

    Publication Year: 2007 , Page(s): 71
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  • 2007 IEEE international workshop on memory technology, design, and testing (MTDT’07)

    Publication Year: 2007 , Page(s): 72
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