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Memory Technology, Design and Testing, 2007. MTDT 2007. IEEE International Workshop on

Date 3-5 Dec. 2007

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Displaying Results 1 - 25 of 26
  • Message from the General Chairs

    Publication Year: 2007, Page(s):ii - iv
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    Freely Available from IEEE
  • System-in-Package design/testing in memory package

    Publication Year: 2007, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (126 KB)

    Summary form only given. Miniaturization, electric performance and cost have drove the package thinner and thinner. System-in-package (SIP) and system-on-chip (SOC) are two competitive solutions. SIP is becoming the mainstream in assembly, which is able to short the design cycle time and speed up the new product introduction, especially in the mobile phone, hand held product and memory products. S... View full abstract»

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  • Future challenges and opportunities of the memory industry

    Publication Year: 2007, Page(s):2 - 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The still ongoing digital revolution of the 21st century has changed the daily life of a great number of people. The explosive growth of the semiconductor industry, which reached about 16% per year in the past, was based on two pillars; the incessant demand for information-related goods and the advance in process & device integration technology, which satisfied the need for enhancing system pe... View full abstract»

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  • High-performance SRAM in nanoscale CMOS: Design challenges and techniques

    Publication Year: 2007, Page(s):4 - 12
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1471 KB) | HTML iconHTML

    This paper reviews the design challenges and techniques of high-performance SRAM in the "End of Scaling" nanoscale CMOS technologies. The impacts of technology scaling, such as signal loss due to leakage, degradation of noise margin due to VT scatter caused by process variations and random dopant fluctuation, and long term reliability degradation such as NBTI, are addressed. Design dire... View full abstract»

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  • Value creation and technological convergence by evolution of embedded non-volatile memory

    Publication Year: 2007, Page(s):13 - 14
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (301 KB)

    Flash-MCU, micro-controller with embedded flash memory storage (eFlash), has seen a tremendous up-surge in real-time control application markets, with assumed 20% CAGR. The programmable code storage provided by eFlash contributes to production cost reduction and real-time adaptive control applications, realizing a value innovation with remarkable cost/value advantage. The diversified advanced eFla... View full abstract»

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  • Variability, margins, and unpredictability: Dealing with uncertainty in SRAM design

    Publication Year: 2007, Page(s): 15
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (398 KB)

    As process technology continues to advance, SRAM design is becoming increasingly critical. Not only does memory occupy a large portion of the design, but memory structures are increasingly susceptible to yield and variability issues than. Classical design validation and margining methods must be extended to cope with new challenges, including low power operation, accurate modeling, blurring lines ... View full abstract»

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  • Scaling trend of the Flash memory for file storage

    Publication Year: 2007, Page(s): 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (101 KB)

    This paper describes the review of flash memory. First, the fundamental device and design characteristics of flash memory are shown. Next, recent developments of flash memory are reviewed. The flash memory cell structure can be classified into two types; floating gate type and charge trap type. Both current technologies are introduced. Third, road map and scaling issues of flash memory are summari... View full abstract»

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  • Future trend of flash memories

    Publication Year: 2007, Page(s):17 - 18
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (315 KB)

    Summary form only given. Flash memories have provided reliable solid-state storage solutions for over twenty years. In the last few years we have seen an explosive growth of NAND flash, fueled by digital camera, USB, MP3, iPhone and numerous new mobile applications. However, this phenomenal boom is silently threatened by scaling limitations intrinsically built into the flash devices. Old challenge... View full abstract»

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  • Embedded SRAM trend in nano-scale CMOS

    Publication Year: 2007, Page(s):19 - 22
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (940 KB) | HTML iconHTML

    This paper describes an SRAM scaling trend in terms of bit-cell size and operating voltage (Vdd) in a nano-scale process generation. The key design solutions to extend a 6T SRAM lifetime are reviewed and discussed including a possible bit cell scaling trend comparing with an 8T SRAM as one of the successors. Each dependency of 3 key margins of write margin (WRM), static noise margin (SNM), and cel... View full abstract»

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  • Process variability considerations in the design of an eSRAM

    Publication Year: 2007, Page(s):23 - 26
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB) | HTML iconHTML

    Process variation constitutes a serious hindrance to the performance of SRAMs, since memories require bigger design margins for their proper operations. In this paper, we propose a new dummy bit line driver structure and its statistical sizing method to reduce the sensitivity of the memory with respect to process variations, while improving the read timing margin. The dummy bit line driver is an e... View full abstract»

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  • A Controllable low-power dual-port embedded SRAM for DSP processor

    Publication Year: 2007, Page(s):27 - 30
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (467 KB) | HTML iconHTML

    In this paper, a low-power embedded memory module is designed for a multi-threaded DSP processor. A co-design of circuit and architecture technique is proposed. The technique includes three circuit schemes: controllable pre-charged bit-line, low voltage bit-line, and controllable data-retention power gating. Because the low-power control signals are generated by the DSP engine, the operating condi... View full abstract»

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  • How far can we go in wireless testing of memory chips and wafers?

    Publication Year: 2007, Page(s):31 - 32
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (309 KB)

    Summary form only given. Test cost has become a significant portion of the cost structure in advanced semiconductor memory products. To address this issue at both the wafer and packaged-chip levels, we propose HOY - a novel wireless test system with enhanced embedded test features. In this talk we will briefly outline Project HOY and the test systems and applications it defines, with focus on memo... View full abstract»

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  • RAMSES-D: DRAM fault simulator supporting weighted coupling fault

    Publication Year: 2007, Page(s):33 - 38
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (465 KB) | HTML iconHTML

    Memory fault simulator is an important tool for memory test sequence optimization. Traditionally, we use fault count to calculate fault coverage. However, it cannot represent accurately the real coupling fault distribution. In this paper, we adopt the concept of weighted coupling fault targeting DRAM. We propose a weighted fault coverage function with assigning weight parameters to coupling faults... View full abstract»

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  • Resilient SRAM design using BIST-assisted Timing Tracking

    Publication Year: 2007, Page(s):39 - 41
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (333 KB) | HTML iconHTML

    In this paper, an SRAM design using BIST-assisted timing-tracking (BITT) scheme to improve parametric yield by 76.7% as compared with the traditional timing-tracking method has been presented. This scheme combines reconfigurable delay line, which is tunable by memory BIST, with dummy bitline timing tracking. Consequently, the timing skew due to cell current fluctuations and imbalanced sense amplif... View full abstract»

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  • Power-gating current test for static RAM in nanotechnologies

    Publication Year: 2007, Page(s):42 - 45
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB) | HTML iconHTML

    Current test resolution is confined by leakage elevation and variation in the nanometer static RAM. In this paper, we develop a novel scheme to highly improve the resolution by applying current test in power-gating sleep mode. A novel fine-grain power-gated adaptive-retention memory cell structure in the double threshold technology is designed for current testability. An LSB-selected decoder is al... View full abstract»

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  • An automatic design for flash memory testing

    Publication Year: 2007, Page(s):46 - 49
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (378 KB) | HTML iconHTML

    Due to the easy implementation and high fault coverage, the march-like algorithms have been used for the flash memory testing. However, the testing complexity of the flash memory testing is mainly dominated by the memory address spaces. Many tremendous human efforts are required to design a built-in self-test test pattern generator for a large capacity of flash memory. To save the design overhead,... View full abstract»

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  • Next-generation non-volatile memory

    Publication Year: 2007, Page(s): 50
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (289 KB)

    Recently, Next-generation non-volatile memories continue to receive great attention due to its scalability, rapid read and write performance, simple structure, and easy incorporation with CMOS process. There are many candidates for ideal non-volatile memory, such as Magnetro-resistive RAM (MRAM), Phase change RAM (PCRAM), and Resistive RAM (RRAM). This talk will discuss the strengths and weaknesse... View full abstract»

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  • The polarity dependence of ONO thickness for wrapped-select-gate (WSG) SONOS memory

    Publication Year: 2007, Page(s):51 - 54
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (455 KB) | HTML iconHTML

    2-bits/cell operation characteristics of WSG-SONOS memory has been fully studied in different ONO thickness. The 2-bits/cell characteristics of WSG-SONOS memory will be determined by tunneling oxide and total ONO thicknesses. Besides, thicker top oxide thickness will contribute to better gate disturbance performance while maintaining the same drain disturbance. We also found that the excellent end... View full abstract»

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  • A novel poly-Si nanowire TFT for nonvolatile memory applications

    Publication Year: 2007, Page(s):55 - 56
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB) | HTML iconHTML

    A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window. View full abstract»

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  • Improving the speed and power of compilable SRAM using dual-mode self-timed technique

    Publication Year: 2007, Page(s):57 - 60
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (362 KB) | HTML iconHTML

    A long bitline precharge time in the write operation and a wide wordline pulse width in the read operation dominate the cycle time of large-capacity compilable SRAMs. A data-dependent bitline leakage current causes timing skew and erodes the sensing margin of conventional replica-column controlled embedded SRAM. A dual-mode self-timed (DMST) technique is proposed to generate two individual timing ... View full abstract»

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  • Vulnerability analysis of secure USB flash drives

    Publication Year: 2007, Page(s):61 - 64
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (588 KB) | HTML iconHTML

    USB flash drive without any security function causes the exposure of private information. So new USB flash drive supported security function was invented to compensate for the problem. In this paper, we analyze vulnerability of 6 famous secure USB flash drives, and demonstrate that password can be exposed on communication between the secure USB flash drive and PC. Also we show the vulnerability on... View full abstract»

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  • Logic-compatible embedded NVM for RFID application

    Publication Year: 2007, Page(s):65 - 66
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (394 KB) | HTML iconHTML

    In this paper, we described the design of logic-process compatible embedded non-volatile memory (NVM) macro for the application of radio frequency identification (RFID). A prototype 1024-bits NVM test chip fabricated by 0.18 mum standard CMOS process is described and characterized. The characterization result shows write power is only 90 uW for write operation and 2 uW @0.5 MHz for read operation.... View full abstract»

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  • An ALU cluster intellectual property for magnetic RAM media applications platform

    Publication Year: 2007, Page(s):67 - 70
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (391 KB) | HTML iconHTML

    The next generation memory, magnetic random access memory (MRAM), is a high-profile choice of embedded memory in modern applications. Features of the novel memory make it suitable for universal memory applications. Besides, as the evolution of information technology, embedded systems with media applications for portable devices are more important in modern life. In both of the perspectives mention... View full abstract»

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  • Author index

    Publication Year: 2007, Page(s): 71
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  • 2007 IEEE international workshop on memory technology, design, and testing (MTDT’07)

    Publication Year: 2007, Page(s): 72
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    Freely Available from IEEE