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26th IEEE VLSI Test Symposium (vts 2008)

April 27 2008-May 1 2008

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  • [Front cover]

    Publication Year: 2008
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  • [Title page i]

    Publication Year: 2008, Page(s): i
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  • [Title page iii]

    Publication Year: 2008, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2008, Page(s): iv
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  • Table of contents

    Publication Year: 2008, Page(s):v - xi
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  • Foreword

    Publication Year: 2008, Page(s): xii
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  • Committee Lists

    Publication Year: 2008, Page(s):xiii - xv
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  • Program Committee

    Publication Year: 2008, Page(s): xvi
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  • Steering Committee

    Publication Year: 2008
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  • list-reviewer

    Publication Year: 2008, Page(s):xviii - xix
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  • Acknowledgements

    Publication Year: 2008, Page(s): xx
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  • Test Technology Technical Council (TTTC)

    Publication Year: 2008, Page(s):xxi - xxiii
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  • Test Technology Educational Program (TTEP) Tutorials

    Publication Year: 2008, Page(s):xxiv - xxvii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    Provides a listing of current committee members and society officers. View full abstract»

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  • Best Paper awards

    Publication Year: 2008, Page(s):xxviii - xxx
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  • Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems

    Publication Year: 2008, Page(s):3 - 8
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (582 KB) | HTML iconHTML

    Time interleaved A/D converters (TIADCs) provide an attractive solution to the realization of analog front ends in high speed communication systems. However, gain mismatch, offset mismatch, and sampling time mismatch between time-interleaved channels limit the performance of TIADCs. This paper presents a low-cost test scheme to measure timing mismatch using an undersampling clock. Our method is ap... View full abstract»

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  • Test Enabled Process Tuning for Adaptive Baseband OFDM Processor

    Publication Year: 2008, Page(s):9 - 16
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (651 KB) | HTML iconHTML

    As channel conditions in wireless communications improve, the noise performance of the baseband DSP processor can be degraded to save power without compromising bit error rate. The degradation of baseband signal noise is achieved by degrading the noise performance (reducing the wordlength and supply voltage) of the various baseband signal processing modules in specific proportions defined by a loc... View full abstract»

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  • Bit-Error Rate Estimation for Bang-Bang Clock and Data Recovery Circuit in High-Speed Serial Links

    Publication Year: 2008, Page(s):17 - 22
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (307 KB) | HTML iconHTML

    Clock and data recovery (CDR) circuits incorporating a bang-bang (BB) phase detector have been widely adopted in high-speed serial links due to their advantages in high speed implementations. However, the heavily non-linear nature of the BB phase detector makes the analysis of the CDR loop difficult. In this paper, we propose a new technique for accurate and efficient estimation of the bit- error ... View full abstract»

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  • How Many Test Patterns are Useless?

    Publication Year: 2008, Page(s):23 - 28
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (382 KB) | HTML iconHTML

    Studies by previous researchers using production test data reported that not all the production test patterns applied detected defective chips. Researchers found that 70% to 90% of their production test patterns seemed useless because these patterns detected no defective chips and they could therefore be removed without impacting test quality. Previous researchers qualitatively explained this find... View full abstract»

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  • Constructing Augmented Multimode Compactors

    Publication Year: 2008, Page(s):29 - 34
    Cited by:  Papers (4)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB) | HTML iconHTML

    In this paper, a new space compactor, called an augmented multimode compactor, is presented. Accordingly, scan chains are separated into groups using t orthogonal partitions. The augmented multimode compactor has three modes such that all scan chains, a group of scan chains and an intersection of two groups of scan chains is selected for compression. Respectively, 1, kt-1 and any number of unknown... View full abstract»

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  • Increasing Output Compaction in Presence of Unknowns Using an X-Canceling MISR with Deterministic Observation

    Publication Year: 2008, Page(s):35 - 42
    Cited by:  Papers (13)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (255 KB) | HTML iconHTML

    Recently, an X-canceling MISR methodology was proposed in Touba (2007) which was based on providing very high probabilistic error coverage by canceling out X's in MISR signatures. This paper investigates a new methodology for using the X-canceling MISR architecture based on deterministically observing scan cells. The two main advantages of the proposed approach are (1) it can provide a higher amou... View full abstract»

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  • IP Session 1C: Highways to Zero-Defects: Industrial Approaches

    Publication Year: 2008, Page(s): 43
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (213 KB)

    Zero defect (ZD) objective is met today with a comprehensive and inter-disciplinary ZD Program that spans across the entire IC development flow. DFT (design for testability) is a critical component of the ZD program and has the potential to increase its utility. While scan and memory BIST are being used effectively, the DFT methodologies around analog, RF, MEMs, high-speed 10 and mixed-signal logi... View full abstract»

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  • Inconsistent Fail due to Limited Tester Timing Accuracy

    Publication Year: 2008, Page(s):47 - 52
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB) | HTML iconHTML

    Delay testing is a technique to determine if a chip will function correctly at a specified frequency. If a chip passes delay tests, it will presumably function at the specified frequency in the field. This paper presents experimental results that show how chips can pass very thorough delay tests and still fail in the field. It is shown that some chips sometimes pass and sometimes fail when the sam... View full abstract»

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  • A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips

    Publication Year: 2008, Page(s):53 - 58
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    Conventional methods to assess the test data volume (TDV) of logic in system-on-chips (SoCs) use intuitive formulae that are often agnostic of the target automatic test equipment (ATE) hardware or the ATE test program compilation process. In this paper, we first show that such ATE-unaware approaches lead to a significant gap between these estimates and the actual tester memory consumed. We also pr... View full abstract»

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  • Basing Acceptable Error-Tolerant Performance on Significance-Based Error-rate (SBER)

    Publication Year: 2008, Page(s):59 - 66
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (398 KB) | HTML iconHTML

    As CMOS scaling continues to decrease and new technologies emerge, feature sizes approach molecular sizes. Due to high defect rates, process variations and quantum effects, manufacturing yields have decreased. To increase the effective yield, error-tolerance, which allows for some defective chips to be employed in systems that can tolerate errors, has been proposed. To support error-tolerance, the... View full abstract»

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  • Diagnosis of Scan Clock Failures

    Publication Year: 2008, Page(s):67 - 72
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (263 KB) | HTML iconHTML

    In this paper we present a fault diagnosis procedure for defects in the scan clock tree. We first identify the candidate clock tree buffers common to failing chains by backtracing. We then evaluate and rank these candidates by forward tracing and simulation. Experimental results show that the proposed procedure provides accurate diagnosis of scan clock failures. View full abstract»

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