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European Test Conference, 1993. Proceedings of ETC 93., Third

Date 19-22 April 1993

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Displaying Results 1 - 25 of 84
  • Proceedings of ETC 93. Third European Test Conference (Cat. No.93TH0494-5)

    Publication Year: 1993
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    Freely Available from IEEE
  • Modular-addition signature analysis for built-in self-test

    Publication Year: 1993 , Page(s): 457 - 465
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (676 KB)  

    The conventional multiple input signature register (MISR) has an average time to alias of 2n (n is the length of the register), i.e., it aliasing probability is 1/2n. This paper presents a new cellular-automaton structure called modular-addition signature analyzer (MASA), which is shown to be an excellent alternative of MISR. It has a much lower hardware overhead than MISR ba... View full abstract»

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  • Essential testability guidelines for current technology

    Publication Year: 1993 , Page(s): 273 - 282
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (696 KB)  

    This paper addresses the testability considerations, both electrical and mechanical, and focuses on requirements of technologies in the 1990s. It provides practical insight into how printed circuit board should be designed to make them testable. Developing discipline in design-for-test practices will inherently provide major savings in time and money in the test development process, reducing overa... View full abstract»

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  • On scan path design for stuck-open and delay fault detection

    Publication Year: 1993 , Page(s): 201 - 210
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (860 KB)  

    A novel scan path design technique is presented, which facilitates the application of two-pattern tests by transition shifting. The scan path is composed based on the test data set as a graph matching problem. For the reduction of the required test application time, a novel reconfigurable scan path architecture is presented, which is synthesized based on the test data set. This reconfigurable scan... View full abstract»

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  • Testing of resistive bridging faults in CMOS flip-flop

    Publication Year: 1993 , Page(s): 530 - 531
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (104 KB)  

    This paper provides an analysis of flip-flop testability with respect to resistive bridging faults. Problems inherent to their detection not encountered in combinational circuits are discussed, and practical solutions are proposed to overcome the main difficulties View full abstract»

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  • A deductive method for simulating transistor stuck-open faults in CMOS circuits

    Publication Year: 1993 , Page(s): 284 - 291
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (524 KB)  

    This paper presents a deductive method for simulating transistor stuck-open faults in CMOS circuits. A distinctive feature of the method is that it deduces all the detected transistor stuck-open faults by a robust test pattern using only one run of fault-free circuit simulation. No explicit simulation of faulty circuits is needed. The behavior of a good or faulty circuit is distinguished by whethe... View full abstract»

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  • Experimental results on aliasing errors in circular BIST design

    Publication Year: 1993 , Page(s): 466 - 474
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (716 KB)  

    Although many analyses on aliasing errors have been reported, no definite experiments has been reported on aliasing probabilities under built-in self-test (BIST) environment. In this paper, the authors present experimental results on the aliasing probability of the circular BIST design technique. Among 23 ISCAS89 benchmark circuits experimented, aliasing errors were detected in only 2 of the 23 ci... View full abstract»

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  • The effect of guardbands on errors in production testing

    Publication Year: 1993 , Page(s): 2 - 7
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (368 KB)  

    Guardbands are often used in production testing when instrumentation inaccuracies are present. Guardbands protect against the error of inadvertently certifying a defective product to be good. Unfortunately, guardbands also increase the amount of good products that are erroneously failed in testing. This paper analyzes the testing error trade-offs due to guardband placement for the case when a manu... View full abstract»

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  • New methods for parallel pattern fast fault simulation for synchronous sequential circuits

    Publication Year: 1993 , Page(s): 532 - 533
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (136 KB)  

    The authors present COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED is based on coupling a parallel pattern simulator with a non-parallel simulator. COMBINED runs substantialy faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator View full abstract»

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  • Current vs. logic testability of bridges in scan chains

    Publication Year: 1993 , Page(s): 392 - 396
    Cited by:  Papers (14)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (248 KB)  

    Comparison between current and voltage testing in a scan-path flip-flop affected by single bridging defects is presented. Defects obtained by inductive fault analysis (IFA) have been classified depending on the location within the scan cell and its electrical behaviour has been simulated using HSPICE. Current (Iddq) testing of zero resistance bridges covers only 92% of the realistic bri... View full abstract»

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  • Fault simulation for synchronous sequential circuits under the multiple observation time testing approach

    Publication Year: 1993 , Page(s): 292 - 300
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (784 KB)  

    The authors describe a fault simulator for synchronous sequential circuits given in gate-level. The simulator uses the multiple observation time testing approach to identify faults detected by a given test sequence, that cannot be identified as detected using a conventional fault simulator. It is shown that a test sequence that does not detect a given fault may still be effective in identifying th... View full abstract»

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  • Functional memory array testing using associative search algorithms

    Publication Year: 1993 , Page(s): 139 - 148
    Cited by:  Patents (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (776 KB)  

    To accelerate functional memory array testing in advanced workstations, a conventional memory array is proposed to be modified using circuit structures known from flag-oriented associative memories. Thus memory array lines can be tested in parallel using associative search operations. All memory chips are tested in parallel using conventional tests. The drastic test speed up due to the new approac... View full abstract»

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  • A pattern skipping method for weighted random pattern testing

    Publication Year: 1993 , Page(s): 418 - 425
    Cited by:  Papers (2)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (656 KB)  

    Conventional stored pattern testing of very large scan design networks is increasingly burdened by the immense volume of pattern data that must be explicitly stored and manipulated for testing. Weighted random pattern testing uses an effective test data coding scheme to reduce the required explicit storage at the expense of increased test time. A novel method is introduced for efficiently skipping... View full abstract»

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  • Random test length for bounded faults in RAMs

    Publication Year: 1993 , Page(s): 149 - 158
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (600 KB)  

    The authors study a very general class of memory faults that includes the usual stuck-at, coupling, and pattern-sensitive faults. This is the class that consists of `bounded faults' that is, faults that involve a bounded number of cells. Some bounded faults are known to require deterministic tests of length proportional to n log2 n, where n is the total number... View full abstract»

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  • Basic boundary-scan for in-circuit test

    Publication Year: 1993 , Page(s): 349 - 354
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (404 KB)  

    Boundary-scan was developed to allow testing without a full bed-of-nails, but many boards have only a few boundary-scan parts, and still require a full bed-of-nails. The manufacturers of those boards are getting many advantages from the use of boundary-scan, including faster model development time for complex parts, faster test run times, faster model and board debug times and much more accurate d... View full abstract»

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  • Interconnect testing for bus-structured systems

    Publication Year: 1993 , Page(s): 476 - 483
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (460 KB)  

    This paper considers the problem of generating test vectors for interconnect testing within a boundary-scan environment. Provision is made for both detection and diagnosis of single and multiple bridging faults and stuck faults on driver and bus lines. The procedures developed cater for all combinations of structures within a board, and allow for the special problems of CMOS elements. The test set... View full abstract»

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  • A model for functional test generation and testability analysis

    Publication Year: 1993 , Page(s): 515 - 516
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (168 KB)  

    An overview has been given of a new approach to functional test generation. The program GESTE permits the generation of symbolic tests by constructing a path through the graph model, establishing, and solving a system of equations and inequalities. The model extracted from a behavioural VHDL description contains control flow and, implicitly, data flow. The behavioural level fault model includes bo... View full abstract»

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  • Modules for gigahertz digital testing of ECL

    Publication Year: 1993 , Page(s): 320 - 328
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (532 KB)  

    A family of high-speed, low-cost multiplexer and data capture circuits is introduced. These hybrid circuits are based on previously introduced principles and are used to extend the upper frequency limits of existing test systems. The modules are based on low-cost ECL technology yet support testing up to about 1 Gpbs. Multiplexers with typical edge rates of 500 ps are demonstrated. Subnanosecond-wi... View full abstract»

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  • On automatic fault isolation using DFT methodology for active analog filters

    Publication Year: 1993 , Page(s): 534 - 535
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (148 KB)  

    DFT methodology for active analog filters based on analog scan structures has been proposed previously. The authors describe an extension of the methodology to automatic fault isolation by means of model-based diagnosis performed by the AI tool CLP. The implemented diagnostic algorithm uses results of measurements of magnitude and phase characteristics for a given frequency in the normal mode and ... View full abstract»

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  • Automated comparison of measured versus expected signals in mixed signal device testing and its effect on fault localization strategies

    Publication Year: 1993
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (100 KB)  

    The comparison of measured versus expected signals is the basic operation of any test process. It becomes a critical task especially when rather noisy contactless measurement techniques are employed for prototype debug and quality assurance purposes. The presentation describes ways of get most reasonable pass/fail decisions in the case of uncertainties View full abstract»

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  • Multiple-domain concurrent and comparative simulation

    Publication Year: 1993 , Page(s): 301 - 310
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (776 KB)  

    Multiple-domain concurrent and comparative simulation (MDCCS), a generalization of concurrent and comparative simulation (CCS), and thus of discrete event simulation, is introduced. MDCCS is a generalization that makes concurrent simulation applicable to virtually every task or problem that can be handled with discrete event simulation View full abstract»

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  • Integration of IEEE 1149.1 with mixed ECL, TTL and differential logic signals

    Publication Year: 1993 , Page(s): 355 - 360
    Cited by:  Patents (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (420 KB)  

    IEEE 1149.1, the Standard Test Access Port and Boundary-Scan Architecture, has been most often applied to TTL-compatible logic circuits. This paper reviews some issues which arise when applying 1149.1 to systems fabricated with integrated circuits (IC's) from mixed, incompatible logic families such as emitter coupled logic (ECL) and TTL-compatible logic; and interconnection systems where, to impro... View full abstract»

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  • A contribution to testing of analog integrated circuits in the DC domain

    Publication Year: 1993 , Page(s): 131 - 137
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (380 KB)  

    A test method for analog circuits is presented which is based upon simple DC measurements that can be performed directly on the wafer. The method handles parameters at various levels, e.g. process, device and circuit parameters. In contrast to other methods that use parameter intervals, the method described obtains a mathematical relation between the parameters, which results in a more powerful de... View full abstract»

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  • Fast and high quality in-circuit test development through expert debug

    Publication Year: 1993 , Page(s): 427 - 433
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (612 KB)  

    Analog in-circuit program generator (APG) technology has improved to a state where the quality of tests written by APGs can hardly be met by tests written by humans. The authors propose a new debug methodology for tests, in which the root cause for tests that fail during debug is diagnosed and repaired. In order to aid the test developer and to cut debug time the authors have developed a debug env... View full abstract»

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  • Methodology of detection of spurious signals in VLSI circuits

    Publication Year: 1993 , Page(s): 491 - 496
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (372 KB)  

    The continuous reduction in scale achieved in microelectronic technology and the increasing switching speed may cause parasitic or spurious signals to appear, due to crosstalk. In this work, scale reduction of interconnections is analyzed, showing the increasing mutual capacitance and a model of crosstalk considering parasitic capacitive coupling is shown. A method for studying the propagation of ... View full abstract»

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