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European Test Conference, 1993. Proceedings of ETC 93., Third

Date 19-22 April 1993

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  • Proceedings of ETC 93. Third European Test Conference (Cat. No.93TH0494-5)

    Publication Year: 1993
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    Freely Available from IEEE
  • Resynthesis for testability of redundant combinational circuits

    Publication Year: 1993, Page(s):511 - 512
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    This paper presents an algorithm to generate circuits which are irredundant for stuck-at fault testing but which preserve all the properties of the original design; then any state-of-the-art ATPG procedure can be applied to the modified network. The algorithm makes use of additional control inputs to convert the redundant AND-OR function of the circuit, represented as the sum of all its prime impl... View full abstract»

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  • Combinational ATPG theorems for identifying untestable faults in sequential circuits

    Publication Year: 1993, Page(s):249 - 253
    Cited by:  Papers (33)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The authors present two theorems for identifying untestable faults in sequential circuits. The first, single-fault theorem, states that if a single fault in a combinational array is untestable then that fault is untestable in the sequential circuit. The array replicates the combinational logic and can have any finite length. The present state inputs of the left-most block are assumed completely co... View full abstract»

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  • Using EDIF in IC testing: experience from the Everest project

    Publication Year: 1993, Page(s):434 - 443
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    Without a standard for describing test vectors, timing and levels it is a cumbersome process to take test data from an ATPG to a simulator or from a simulator to an ATE. From the electronic industries in Europe, USA and Japan, many people have worked together under the auspices of the EIA to create a provisional test view in EDIF (electronic design interchange formats). This paper evaluates an ear... View full abstract»

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  • Functional validation methods for VLSI-based systems

    Publication Year: 1993, Page(s):509 - 510
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    This paper presents a new methodology for comprehensive high level design verification of audio and video DSP ICs. The presented method allows ICs to be tested in a `near-application' mode of operation using `real-life' data to check the functional correctness of the design View full abstract»

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  • Algebraic ATPG of combinational circuits using binary decision diagrams

    Publication Year: 1993, Page(s):240 - 248
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (780 KB)

    The increasing size and complexity of VLSI circuits has brought testing and design for testability into the mainstream of the design process. However, VLSI designers have been reluctant to incorporate ATPG techniques into their environments because ATPG systems either take inordinate amounts of time in generating tests for faults or do not achieve significant fault coverage in the allotted time. U... View full abstract»

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  • Fast and high quality in-circuit test development through expert debug

    Publication Year: 1993, Page(s):427 - 433
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    Analog in-circuit program generator (APG) technology has improved to a state where the quality of tests written by APGs can hardly be met by tests written by humans. The authors propose a new debug methodology for tests, in which the root cause for tests that fail during debug is diagnosed and repaired. In order to aid the test developer and to cut debug time the authors have developed a debug env... View full abstract»

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  • Defect level as a function of fault coverage and yield

    Publication Year: 1993, Page(s):507 - 508
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    An extension of the well known formula relating yield, fault coverage and defect level has been derived by removing the hypothesis of equally likely faults and exploiting the concept of critical area to evaluate the probabilities of individual faults, under the hypothesis of Poisson's yield model. A generalized weighted fault coverage figure has been introduced with reference to realistic faults a... View full abstract»

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  • Mixed-signal automatic test program generation

    Publication Year: 1993, Page(s):528 - 529
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (124 KB)

    A novel program is presented which automates the generation of test programs for analogue and mixed-signal integrated circuits. The tests are entered graphically by the IC designer, providing a link between the design and test stages in IC development. The program developed can be used with any schematic entry front end capable of writing EDIF 200 netlists. The tests entered are checked by the pro... View full abstract»

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  • Phase coherent, event synchronized test system architecture

    Publication Year: 1993, Page(s):312 - 319
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    It is increasingly difficult to provide test conditions utilising ATE equipment which correlate with applications conditions in which devices are designed to operate. This paper suggests functional parameters and an architecture conductive to successful and economical ATE testing of time differentiated functionality View full abstract»

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  • Incoming inspection of FPGA's

    Publication Year: 1993, Page(s):371 - 377
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A fault free field programmable array (FPGA) is essential for prototyping design. The authors present a test method that will allow a designer to quickly and efficiently test the FPGA so that he can with confidence know that any errors are design errors and are not due to the presence of manufacturing faults in the FPGA. The fault method is based on a divide and conquer approach for testing regula... View full abstract»

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  • Test pattern generation for multiple stuck-at faults

    Publication Year: 1993, Page(s):230 - 239
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (872 KB)

    A new method to generate test patterns for multiple stuck-at faults in combinational circuits is presented. All multiple faults of any multiplicity are assumed present in the circuit and one does not have to resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. The authors try to generate test conditions that propagate the effect of the t... View full abstract»

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  • On the diagnosability of DNMR testing

    Publication Year: 1993, Page(s):517 - 518
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    Dynamic N-Modular Redundancy (DNMR), with interstitially placed voters, provides a testing technique with low area overhead and high diagnosability, applicable for fabrication-time and on-line real traffic testing of fault-tolerant processing arrays. Improved diagnosability is obtained not only by increasing the voting level, but also by using different test propagation methods. Also, diagnosis is... View full abstract»

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  • Current vs. logic testability of bridges in scan chains

    Publication Year: 1993, Page(s):392 - 396
    Cited by:  Papers (14)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (248 KB)

    Comparison between current and voltage testing in a scan-path flip-flop affected by single bridging defects is presented. Defects obtained by inductive fault analysis (IFA) have been classified depending on the location within the scan cell and its electrical behaviour has been simulated using HSPICE. Current (Iddq) testing of zero resistance bridges covers only 92% of the realistic bri... View full abstract»

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  • A pattern skipping method for weighted random pattern testing

    Publication Year: 1993, Page(s):418 - 425
    Cited by:  Papers (5)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (656 KB)

    Conventional stored pattern testing of very large scan design networks is increasingly burdened by the immense volume of pattern data that must be explicitly stored and manipulated for testing. Weighted random pattern testing uses an effective test data coding scheme to reduce the required explicit storage at the expense of increased test time. A novel method is introduced for efficiently skipping... View full abstract»

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  • Testing of analogue to digital converter macros in ASICs

    Publication Year: 1993, Page(s):505 - 506
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    The approach to testing mixed ASICs is initially to research the specification and performance of available low-cost analogue CMOS macros. A simple self-test technique for the analogue to digital converter macro, using the available macros, is outlined and the results evaluated. Full tests for the converter macro are also performed View full abstract»

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  • FNSIM: a functional fault simulator for efficient testability analysis

    Publication Year: 1993, Page(s):526 - 527
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    The problems of designing a versatile fault simulator for circuits lacking low-level structural details (no gate-level or transistor-level description) are addressed. Techniques of functional fault-modelling for test generation have been adapted to fault simulation. Methods for efficient handling of undetermined states are considered. A C++ implementation has been produced View full abstract»

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  • Concurrent error detection of CMOS digital and analog faults

    Publication Year: 1993, Page(s):74 - 81
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    The authors present a novel approach to designing TSC (totally self-checking) CMOS circuits, considering transistor stuck-on faults. Their approach is delineated by a design-for-testability (DFT) technique, which requires a very small constant number of extra transistors, coupled with a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry can defect the faults in t... View full abstract»

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  • A framework for test quality assessment

    Publication Year: 1993, Page(s):8 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    This paper describes a novel framework for estimating the quality level of tests for digital circuits, using realistic fault models which represent faults that are likely to occur. The framework contains test pattern generation and fault simulation programs, automated logic synthesis and silicon compilation programs, and an inductive fault analysis (IFA) program. The framework is used to produce e... View full abstract»

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  • Fault coverage and yield predictions: do we need more than 100% coverage?

    Publication Year: 1993, Page(s):180 - 187
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    The influence of non-random defect distributions and of non-modelled faults on the behavior of the cumulative chip fallout as a function of the cumulative fault coverage is discussed. The theory is applied to published yield data and a novel explanation of the deviation of these data from the classical Williams-Brown theory is presented View full abstract»

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  • Multiple-domain concurrent and comparative simulation

    Publication Year: 1993, Page(s):301 - 310
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    Multiple-domain concurrent and comparative simulation (MDCCS), a generalization of concurrent and comparative simulation (CCS), and thus of discrete event simulation, is introduced. MDCCS is a generalization that makes concurrent simulation applicable to virtually every task or problem that can be handled with discrete event simulation View full abstract»

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  • Implementing BIST and boundary-scan in a digital signal processor ASIC for radiocommunication applications

    Publication Year: 1993, Page(s):361 - 369
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    This paper describes the testability strategy used in the design of a complex DSP VLSI for radiocommunication applications. A solution based on the use of a micro-coded BIST has been chosen. The IEEE 1149.1 boundary scan test is used to control the chip self-test. The BIST structures provide go/no-go flags as well as diagnosis capabilities using signature analysis View full abstract»

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  • On the testability of FFT arrays

    Publication Year: 1993, Page(s):219 - 228
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    This paper presents new approaches for testing VLSI array architectures used in the computation of the complex N-point fast Fourier transform. Initially, an unrestricted single cell-level fault model is considered. The first proposed approach is based on a process whose complexity is independent (or C- as constant) of the number of cells in the FFT architecture. This is accomplished by sh... View full abstract»

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  • A new and secure selftest scheme for block cipher implementations

    Publication Year: 1993, Page(s):501 - 502
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (140 KB)

    A well-known theorem of communications theory has been applied to show the inherent test-friendliness of implementations of modern block ciphers. The resulting principle is the basis for the implementation of an efficient selftest scheme in a VLSI block cipher design in order to meet binding security requirements of cryptographic equipment View full abstract»

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  • A fault signature approach to analog devices testing

    Publication Year: 1993, Page(s):116 - 121
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    A time domain technique for go-no-go testing of linear analog devices has been analysed in order to identify the conditions that maximise its sensitivity to structural and drift failures. The application to a commercial CMOS operational amplifier showing its ability to cover almost all of the assumed faults, and the ease of generation of the test stimulus on standard ATE equipments, suggest variab... View full abstract»

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