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Proceedings ETC 93 Third European Test Conference

19-22 April 1993

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  • Proceedings of ETC 93. Third European Test Conference (Cat. No.93TH0494-5)

    Publication Year: 1993
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    Freely Available from IEEE
  • Analysis of voltage forcing consequences during in-circuit testing

    Publication Year: 1993, Page(s):536 - 537
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    In-circuit testing enables one to verify the functionality of electrical connections on the board and of components mounted on it. Despite its different drawbacks, mainly related to the potential damage that can be caused to the active components mounted on the board, this technique is still the most commonly used one as it presents almost no limitation concerning the kind of devices to be tested ... View full abstract»

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  • Emitter coupled logic testability analysis and comparison with CMOS & BiCMOS circuits

    Publication Year: 1993, Page(s):263 - 272
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    The logic behavior and performance of an ECL OR/NOR gate under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage. Performance degradation faults such as delay, current and voltage transfer characteristics (VTC) or noise margin (NM) faults are ana... View full abstract»

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  • Functional level testability analysis for digital circuits

    Publication Year: 1993, Page(s):545 - 546
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (164 KB)

    A general approach is proposed for calculating controllabilities and observabilities of signals in sequential and combinational circuits at the functional level. The methods and algorithms are based on alternative graphs which are an extension of binary decision diagrams. The algorithms are general and can be easily adjusted for calculation of different testability measures. A structured expressio... View full abstract»

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  • On automatic fault isolation using DFT methodology for active analog filters

    Publication Year: 1993, Page(s):534 - 535
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    DFT methodology for active analog filters based on analog scan structures has been proposed previously. The authors describe an extension of the methodology to automatic fault isolation by means of model-based diagnosis performed by the AI tool CLP. The implemented diagnostic algorithm uses results of measurements of magnitude and phase characteristics for a given frequency in the normal mode and ... View full abstract»

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  • Testing interconnects: a pin adjacency approach

    Publication Year: 1993, Page(s):484 - 490
    Cited by:  Papers (17)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    This paper looks at a new fault model used for shorts between nets on a PCB, the pin-adjacency fault model, and the implementation of two algorithms. The pin-adjacency detection and diagnosis algorithms for detecting and diagnosing these bridging faults. The authors represent the nets and their likelihood to short as a graph, and in conjunction with the new algorithms are able to generate reduced ... View full abstract»

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  • I-path analysis

    Publication Year: 1993, Page(s):255 - 262
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    A circuit at the register transfer level is denoted as an RTL circuit. The paper describes a method for extracting the RTL circuit structure from the circuit formal description, using the I-path concept. The way of representing the RTL circuit structure by a labelled directed graph where nodes represent components and arcs represent connections between them, is presented. Labels identifying the co... View full abstract»

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  • The effect of guardbands on errors in production testing

    Publication Year: 1993, Page(s):2 - 7
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    Guardbands are often used in production testing when instrumentation inaccuracies are present. Guardbands protect against the error of inadvertently certifying a defective product to be good. Unfortunately, guardbands also increase the amount of good products that are erroneously failed in testing. This paper analyzes the testing error trade-offs due to guardband placement for the case when a manu... View full abstract»

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  • Modelling delay in symbolic test for data paths with partial scan

    Publication Year: 1993, Page(s):543 - 544
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    The problem of handling (pipeline) delay in data paths using a symbolic test methodology is addressed. The authors show that the delay in the incomplete scan path architecture, where only a subset of the registers is included in the scan path in order to eliminate the feedback loops, can be easily modelled and taken into account in the (combinational) symbolic test pattern generator. The pith of t... View full abstract»

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  • New methods for parallel pattern fast fault simulation for synchronous sequential circuits

    Publication Year: 1993, Page(s):532 - 533
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB)

    The authors present COMBINED, a super fast fault simulator for synchronous sequential circuits. COMBINED is based on coupling a parallel pattern simulator with a non-parallel simulator. COMBINED runs substantialy faster on ISCAS-89 benchmark circuits than a state-of-the-art single fault propagation simulator View full abstract»

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  • An approach to mixed circuits testing

    Publication Year: 1993, Page(s):503 - 504
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    A test stimuli generation and a signature analysis method are proposed for a mixed mode circuits. The processes are based on a catastrophic fault model simulated at the transistor level, and on a measure of the transient response of the current used by the circuit when applying the stimuli. A built-in dynamic current sensor is proposed in order to perform the transient analysis of the current used... View full abstract»

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  • Multiple-domain concurrent and comparative simulation

    Publication Year: 1993, Page(s):301 - 310
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (776 KB)

    Multiple-domain concurrent and comparative simulation (MDCCS), a generalization of concurrent and comparative simulation (CCS), and thus of discrete event simulation, is introduced. MDCCS is a generalization that makes concurrent simulation applicable to virtually every task or problem that can be handled with discrete event simulation View full abstract»

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  • Interconnect testing for bus-structured systems

    Publication Year: 1993, Page(s):476 - 483
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    This paper considers the problem of generating test vectors for interconnect testing within a boundary-scan environment. Provision is made for both detection and diagnosis of single and multiple bridging faults and stuck faults on driver and bus lines. The procedures developed cater for all combinations of structures within a board, and allow for the special problems of CMOS elements. The test set... View full abstract»

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  • Incoming inspection of FPGA's

    Publication Year: 1993, Page(s):371 - 377
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    A fault free field programmable array (FPGA) is essential for prototyping design. The authors present a test method that will allow a designer to quickly and efficiently test the FPGA so that he can with confidence know that any errors are design errors and are not due to the presence of manufacturing faults in the FPGA. The fault method is based on a divide and conquer approach for testing regula... View full abstract»

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  • Combinational ATPG theorems for identifying untestable faults in sequential circuits

    Publication Year: 1993, Page(s):249 - 253
    Cited by:  Papers (33)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    The authors present two theorems for identifying untestable faults in sequential circuits. The first, single-fault theorem, states that if a single fault in a combinational array is untestable then that fault is untestable in the sequential circuit. The array replicates the combinational logic and can have any finite length. The present state inputs of the left-most block are assumed completely co... View full abstract»

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  • A framework for test quality assessment

    Publication Year: 1993, Page(s):8 - 16
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    This paper describes a novel framework for estimating the quality level of tests for digital circuits, using realistic fault models which represent faults that are likely to occur. The framework contains test pattern generation and fault simulation programs, automated logic synthesis and silicon compilation programs, and an inductive fault analysis (IFA) program. The framework is used to produce e... View full abstract»

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  • FNSIM: a functional fault simulator for efficient testability analysis

    Publication Year: 1993, Page(s):526 - 527
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    The problems of designing a versatile fault simulator for circuits lacking low-level structural details (no gate-level or transistor-level description) are addressed. Techniques of functional fault-modelling for test generation have been adapted to fault simulation. Methods for efficient handling of undetermined states are considered. A C++ implementation has been produced View full abstract»

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  • Testing crossbar switch interconnection networks

    Publication Year: 1993, Page(s):540 - 542
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    The author presents methods of testing crossbar switches in multiprocessor environment. Implementation problems of assuring appropriate test controllability and observability has been considered and referred to popular crossbar switches with static and dynamic interconnection strategies View full abstract»

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  • RT level test scheduling

    Publication Year: 1993, Page(s):499 - 500
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    The paper describes a new model of exploiting parallelism in testing of VLSI circuits. A circuit at the register transfer level is denoted as an RTL circuit. The model utilizes the concept of TACG (test application conflict graph). For the testing process the resource utilization model was defined and used for the TACG construction. The problem of concurrent test application is transformed to the ... View full abstract»

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  • On scan path design for stuck-open and delay fault detection

    Publication Year: 1993, Page(s):201 - 210
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (860 KB)

    A novel scan path design technique is presented, which facilitates the application of two-pattern tests by transition shifting. The scan path is composed based on the test data set as a graph matching problem. For the reduction of the required test application time, a novel reconfigurable scan path architecture is presented, which is synthesized based on the test data set. This reconfigurable scan... View full abstract»

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  • Testing of resistive bridging faults in CMOS flip-flop

    Publication Year: 1993, Page(s):530 - 531
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    This paper provides an analysis of flip-flop testability with respect to resistive bridging faults. Problems inherent to their detection not encountered in combinational circuits are discussed, and practical solutions are proposed to overcome the main difficulties View full abstract»

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  • Methodology of detection of spurious signals in VLSI circuits

    Publication Year: 1993, Page(s):491 - 496
    Cited by:  Papers (19)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (372 KB)

    The continuous reduction in scale achieved in microelectronic technology and the increasing switching speed may cause parasitic or spurious signals to appear, due to crosstalk. In this work, scale reduction of interconnections is analyzed, showing the increasing mutual capacitance and a model of crosstalk considering parasitic capacitive coupling is shown. A method for studying the propagation of ... View full abstract»

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  • MixTest: a mixed signal extension to the HP82000

    Publication Year: 1993, Page(s):444 - 449
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    MixTest is a mixed signal extension to a digital test system. The system is based on the VXI `instrument on a card' system. It is intended to verify mixed signal ICs for consumer electronic applications such as DCC and HDTV. The system uses the concept of virtual instruments employed in conjunction with the digital capabilities of the HP82000 digital test system View full abstract»

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  • Towards a mixed-signal testability bus standard P1149.4

    Publication Year: 1993, Page(s):58 - 65
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (492 KB)

    A Working Group of the IEEE has been working towards the development of a standard testability structure to be built into mixed-signal chips. The structure is intended to be used to facilitate the testing of mixed-signal circuits at all levels from chip to system, and will form part of the IEEE 1149 set of Standards. This paper reviews the progress that has been made by 1993, and indicates the kin... View full abstract»

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  • A model for functional test generation and testability analysis

    Publication Year: 1993, Page(s):515 - 516
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    An overview has been given of a new approach to functional test generation. The program GESTE permits the generation of symbolic tests by constructing a path through the graph model, establishing, and solving a system of equations and inequalities. The model extracted from a behavioural VHDL description contains control flow and, implicitly, data flow. The behavioural level fault model includes bo... View full abstract»

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