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# Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems

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• ### Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems

Publication Year: 1994
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• ### Systolic modular VLSI architecture for multi-model neural network implementation

Publication Year: 1994, Page(s):118 - 124
Cited by:  Papers (1)
| | PDF (563 KB)

Reviews the basic principles to be considered when mixed analog/digital alternatives for implementing neural models are considered. Starting from a generic systolic architecture, the authors adapt its internal structure in order to permit the modular implementation of a wide range of artificial neural network models. After analyzing the basic computational resources required by the considered neur... View full abstract»

• ### Feedforward ANN for 2-1 fixed point ALUs

Publication Year: 1994, Page(s):156 - 162
| | PDF (510 KB)

Investigates the possibility of constructing fixed point units using feedforward neural networks. The authors investigate the possibility of constructing small depth neural networks for operations usually defined in general purpose computer architectures. In particular the authors show that fixed operations require no more depth than the networks for binary addition. The authors show that depth-3 ... View full abstract»

• ### An analog VLSI massively parallel module for low-level cortical processing in machine vision

Publication Year: 1994, Page(s):207 - 211
Cited by:  Papers (1)  |  Patents (1)
| | PDF (387 KB)

A new approach to analog VLSI implementations of algorithms for visual cortical processing is presented. Specifically, we introduce a massively parallel architecture, organized as a planar resistive network with voltage controlled current generators locally connected to model interaction schemata responsible for specific sensitivities in cortical neurons. We demonstrate the feasibility of this app... View full abstract»

• ### RA: an analog neurocomputer for the synchronous Boltzmann machine

Publication Year: 1994, Page(s):449 - 455
Cited by:  Papers (1)
| | PDF (739 KB)

The Random Analog (RA) Neurocomputer runs synchronous Boltzmann machines dedicated to real time visual pattern recognition. Its architecture achieves scalability and modularity thanks to a linear array of analog processing modules linked by a high bandwidth interconnection network, a controller, and a front end running a high level user interface. A prototype with 128 input neurons and 64 active n... View full abstract»

• ### Author index

Publication Year: 1994, Page(s):456 - 457
| PDF (113 KB)
• ### A continuous-time cellular neural network chip for direction-selectable connected component detection with optical image acquisition

Publication Year: 1994, Page(s):383 - 391
Cited by:  Papers (1)
| | PDF (924 KB)

This paper presents a continuous-time Cellular Neural Network (CNN) chip for the application of Connected Component Detection (CCDet). Projection direction can be selected among four different possibilities. Every cell (or pixel) in the 32×32 array includes a photosensor circuitry and an automatic tuning circuitry to adapt to average environmental illumination. Electrical image uploading is ... View full abstract»

• ### Matching properties of CMOS SOI transistors

Publication Year: 1994, Page(s):134 - 137
Cited by:  Papers (1)  |  Patents (2)
| | PDF (376 KB)

Analog implementations of neural networks have shown promising results; the main drawback of such techniques is the limited accuracy available in standard analog technologies. A test circuit composed of 256 N-channel and P-channel transistors has been designed and tested in an SOI (Silicon-On-Insulator) CMOS 3 μm technology. This paper describes the matching properties of these current sources.... View full abstract»

• ### Fuzzy associative memory by means FPGA's

Publication Year: 1994, Page(s):301 - 307
Cited by:  Patents (1)
| | PDF (452 KB)

The authors introduce a programmable fuzzy associative memory, that has been designed by means of FPGAs. For this design the authors have made use of pipeline techniques, obtaining a short reading time of the memory, and a small size of the architecture. This first version has been implemented by means of three blocks: similarity measure module, arrangement module and control unit View full abstract»

• ### Low power intracardiac electrogram classification using analogue VLSI

Publication Year: 1994, Page(s):376 - 382
| | PDF (588 KB)

A system has been developed for the classification of intracardiac electrograms (ICEG). The system is comprised of an analogue VLSI neural network, an implantable cardioverter defibrillator (ICD) and a PC based software training environment. Analogue implementation techniques were chosen to meet the strict power and area requirements of implantable systems. The robustness of the neural network arc... View full abstract»

• ### Current mode cellular neural network with digitally adjustable template coefficients

Publication Year: 1994, Page(s):268 - 272
Cited by:  Papers (9)
| | PDF (356 KB)

A current mode implementation is presented for a cellular neural network (CNN) with digitally controllable coefficients. The controllability is achieved by applying proper bias voltages to cascode current mirrors. The test circuit is a 1×5 CNN fabricated in a 1.2 μm CMOS process. Measurement results are reported for connected component, shadow and holefiller templates View full abstract»

• ### Circuits and algorithms for adaptive neuro-fuzzy analog chips

Publication Year: 1994, Page(s):331 - 338
Cited by:  Papers (1)
| | PDF (568 KB)

This paper presents adaptive circuit blocks and related learning algorithms to design neuro/fuzzy inference systems using analog integrated circuits in CMOS, standard VLSI technologies. Proposed circuit building blocks are arranged in a layered architecture composed of five layers: fuzzification, T-norm, normalization, consequent, and output. Inference is performed using Takagi and Sugeno's if-the... View full abstract»

• ### RAN2SOM: a reconfigurable neural network architecture based on bit stream arithmetic

Publication Year: 1994, Page(s):294 - 300
Cited by:  Patents (1)
| | PDF (496 KB)

We introduce the RAN2SOM (Reconfigurable Architecture Neural Networks with Serially Operating Multipliers) architecture, a neural net architecture with a reconfigurable interconnection scheme based on bit stream arithmetic. RAN2SOM nets are implemented using field programmable gate array logic. By conducting the training phase in software and executing the actual application ... View full abstract»

• ### A system for high-speed pattern recognition and image analysis

Publication Year: 1994, Page(s):364 - 374
Cited by:  Papers (2)
| | PDF (964 KB)

A mixed analog/digital chip (ANNA) for fast 2-d convolution and matrix-vector multiplication has been developed (peak speed 20,000 MOPS). Two of these chips have been integrated on a 6U VME board, to serve as a high-speed platform for a wide variety of algorithms used in neural-network applications as well as in image analysis. The system has been tested for such tasks as character recognition, no... View full abstract»

• ### A digital implementation of self-organizing maps

Publication Year: 1994, Page(s):260 - 267
Cited by:  Papers (6)
| | PDF (628 KB)

A digital implementation of self-organizing maps is presented. The chip designed includes 32 neurons with 1024 16-bit weights and 8-bit inputs. Each neutron performs bit-serial processing to minimize the occupied silicon area. Several chips can be interconnected to expand the number of neurons in the network. The number of inputs per neuron depends on the internal weight memory size. The dimension... View full abstract»

• ### NET32K high speed image understanding system

Publication Year: 1994, Page(s):413 - 421
Cited by:  Papers (3)  |  Patents (6)
| | PDF (760 KB)

Two NET32K neural-network chips are integrated on a board system with an SBus interface, to serve as a high speed image analysis platform. The system is optimized for convolutional networks. Up to 64 Kernels of size 16×16 pixels are scanned simultaneously over an image. In this way, simple geometric shapes are extracted from an image, representing its content in a compact form. A standard pr... View full abstract»

• ### Continuous-time analog defuzzifier for product-sum based implementations

Publication Year: 1994, Page(s):324 - 330
| | PDF (368 KB)

An analog defuzzifier using arithmetic product and sum is proposed. Instead of the separate computation required in MIN/MAX based implementations, conclusion and defuzzification can be simultaneously realized by a simple aggregation of analog multipliers in which the relative positions of the output membership functions can also be continuously varied, thus allowing its use in adaptive fuzzy and n... View full abstract»

• ### FPGA implementation of artificial neural networks: an application on medical expert systems

Publication Year: 1994, Page(s):287 - 293
Cited by:  Papers (9)
| | PDF (484 KB)

In this paper, the FPGA implementation of an Artificial Neural Networks (ANNs) composition for a Medical Expert System (MES) focused on pulmonary diseases is discussed. Using a specially designed neuron based on pipelined bit-serial arithmetic and a successful approximation of its determinant sigmoid function, a computation module has been structured that can accommodate eight (8) neurons in one F... View full abstract»

• ### Massively parallel VLSI-implementation of a dedicated neural network for anomaly detection in automated visual quality control

Publication Year: 1994, Page(s):354 - 363
Cited by:  Papers (2)  |  Patents (3)
| | PDF (1340 KB)

In this work we will present the VLSI-implementation of a dedicated neural network architecture which we have developed in prior work for anomaly detection in automated visual industrial quality control. The network, denoted as NOVAS performs a filtering of inspection images and highlights defects or anomalies in an isomorphic image representation, allowing the detection and localisation of faults... View full abstract»

• ### VLSI design of radial functions hardware generator for neural computations

Publication Year: 1994, Page(s):252 - 259
Cited by:  Papers (2)
| | PDF (488 KB)

Multidimensional radial functions (RFs) are widely used in several neural network schemes and may have interesting applications also in fuzzy logic based systems. Unfortunately their classical look-up table hardware implementation needs an external board that does not allow high speed real world applications. In this paper we introduce a new approach in which approximate RFs are completely generat... View full abstract»

• ### Fuzzy interpretable dynamically developing neural networks with FPGA based implementation

Publication Year: 1994, Page(s):226 - 234
Cited by:  Papers (2)  |  Patents (6)
| | PDF (700 KB)

Methods of hardware implementation for fast, transparent and efficient neural classifiers based on dynamically developing network structures are presented. The neural networks and the learning algorithms are modified for easy hardware implementation. The proposed methods are tested with several application examples. The hardware implementability is verified by simulating the parallel parts in VHDL... View full abstract»

• ### Architecture of a 50 MFIPS fuzzy processor and the related 1 μm VLSI CMOS digital circuits

Publication Year: 1994, Page(s):125 - 133
Cited by:  Papers (6)
| | PDF (632 KB)

This paper deals with two problems: the first concerns the design of the HW architecture of a high speed fuzzy processor that can work at 50 Mega fuzzy inference per second (MFIPS). It has eight 7 bit inputs and one 7 bit output. It is foreseen to apply it to a trigger device in HEP (High Energy Physics) experiments, the second one concerns the 1 μm CMOS VLSI design of the fuzzification and inf... View full abstract»

• ### Learning with analogue VLSP MLPs

Publication Year: 1994, Page(s):67 - 76
Cited by:  Papers (6)
| | PDF (800 KB)

Much work has been undertaken to demonstrate the advantages of analogue VLSI for implementing neural architectures. This paper attempts to address the issues concerning in-situ' learning with analogue VLSI multi-layer perceptron (MLP) networks. In particular, the authors propose that chip-in-the-loop' learning is, at the very least, necessary to overcome typical analogue process variations and t... View full abstract»

• ### Performance of digital neuro-computers

Publication Year: 1994, Page(s):87 - 93
Cited by:  Papers (3)
| | PDF (588 KB)

This paper deals with performance measurement and evaluation of digital neuro-computers. We discuss the constraints introduced by hardware implementations. A revisited definition of computer speed-up is then proposed, taking into account both the traditional notion of parallelization speed-up and the algorithmic precision of the machines. Finally we show, on the example of the Kohonen feature map ... View full abstract»

• ### A comparison between analog and pulse stream VLSI hardware for neural networks and fuzzy systems

Publication Year: 1994, Page(s):77 - 86
Cited by:  Papers (5)
| | PDF (740 KB)

This paper presents coherent pulse width modulation as a computing technique used in hardware implementations of artificial neural systems. Its performance are analyzed theoretically and simulated. Results are compared against those of analog ones, for the two specific cases of a multiplier and a data transmission line. It is shown that the two methods are comparable in terms of performance, altho... View full abstract»