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Electronic Materials and Packaging, 2007. EMAP 2007. International Conference on

Date 19-22 Nov. 2007

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Displaying Results 1 - 25 of 70
  • Amkor technologies [advertisement]

    Publication Year: 2007 , Page(s): 1 - 4
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  • QFN assembly dilemma - solutions

    Publication Year: 2007 , Page(s): 1 - 5
    Cited by:  Papers (1)
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    In the competition of market share of quad flat no-lead (QFN) package, there were several improvement methods being utilized, such as leadframe design for higher density, cheaper tape, and more functionalities per chip (with smaller package size, larger die, and smaller pad size). Most of these improvement methods created extremely weak die attach and wire bonding structures, causing significant amount of issues in production of QFN packages. Some of the new die attach requirements had caused the ratio of die size to flag size reaching almost one for epoxy dispensing process. This allowed larger die to go inside the QFN package, but epoxy quality control became very stringent. Meanwhile, half etched flag and lead structures caused further amplification of resonance effect, generating more stress inside bonded wires. Eventually, wire weak points, neck or heel started showing stress effects, until failing at actual applications. By utilizing special statistical analysis, each significant factor was screened out, and then combined into optimum interaction. With acid testing method, optimum interaction was proven to be robust and stable in production. View full abstract»

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  • Reliability analysis of copper interconnection in system-in-package structure

    Publication Year: 2007 , Page(s): 1 - 5
    Cited by:  Papers (9)
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    The system-in-package (SiP) is one of the popular designs to meet the trend of integrated circuit (IC) development. It is known for its small size, light weight, and multiple functionality. In this paper, a radio frequency front end module (RF-FEM) incorporated with the novel wafer-level chip scale package (WLCSP) technology is investigated. Generally the solder joints in WLCSP are the weakest portions due to the CTE mismatch between the PCB board and the package. For the SiP structure investigated, the filler polymer is treated as a good stress buffer layer to relax most CTE-mismatch-induced thermal stress. However, the interconnection laminated within the filler polymer is pulled by the expansion of the polymer with relatively higher thermal stresses. The reliability of copper interconnection between chips then becomes a serious issue for the SiP structure. Finite element analysis (FEA) was applied to evaluate the stress distribution of the SiP structure under the thermal loading from 25degC to 125degC. Both package-level and board- level structures are studied. The same fatigue phenomenon is observed in similar package structures [C. yuan et al., 2006; H.P. Wei et al., 2006; M.C. Yew et al., 2006]. Investigating further, two failure mechanisms are disclosed in the package-level structure and board-level structure, respectively. The first failure mechanism is due to the CTE mismatch among the copper interconnections, filler polymer, and chips. Meanwhile, the second failure mechanism is due to the expansion of the filler polymer which will pull the copper interconnection, thereby aggravating the stress concentration behavior, especially at the chip/polymer edge. To reduce the effect of CTE mismatch, several parametric studies are performed to enhance the reliability of copper interconnections. Finally, a compromised optimal distance is found to minimize the stress concentration of vias on chips would be decided. View full abstract»

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  • Warpage analysis of an LCD panel under thermo-mechanical and hygro-mechanical stress

    Publication Year: 2007 , Page(s): 1 - 7
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    A polarizing plate, which is an important part of a liquid crystal display panel (LCD), is made by sandwiching an organic polarizer between protecting films. An organic polarizer is both a hygroscopic and orthotropic material. The hygroscopic swelling and drying shrinkage of the organic polarizer can cause the polarizing plate to crack and the liquid crystal display panel to warp. The diffusion coefficient and Henry's law coefficient were measured using a thermo-gravimetric analyzer (TGA) under controlled humidity, while the coefficient of moisture expansion (CME) was measured using a thermo-mechanical analyzer (TMA), also under controlled humidity. The thermo-mechanical and hygro-mechanical deformation of a polarizing plate was analyzed using the finite element method (FEM). This analysis was performed as follows. The distribution of the moisture concentration was analyzed according to Fick's law. The equation of Fick's law is similar to that of the transient heat conduction, and the FEM for the transient heat conduction was utilized for the transient diffusion analysis. The hygro-mechanical analysis was then carried out in a way similar to the thermal stress analysis. Thermal stress was analyzed separately using the FEM. Finally, the obtained hygro-mechanical strain and stress were added to the thermal strain and stress, respectively. The analyzed displacement of a polarizing plate using the CMEs of a polarizer and protecting films corresponds to the measured displacement. The warpage of a liquid crystal display panel sometimes causes light leakage along the frame of the display panel due to contact of the display panel with the bezel of the frame. The warpage was analyzed according to the thermo-mechanical strain and the hygro- mechanical strain. View full abstract»

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  • Warpage control of wireless LAN SiP during manufacturing process

    Publication Year: 2007 , Page(s): 1 - 4
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    In this study, the warpage of WLAN strip after reflow process, which contains 7times5 WLAN modules, is considered. 3D thermo-mechanical FEM simulation is carried out to find out the warpage distribution and maximum warpage after reflow process. Experimental investigation on the warpage measurement of the package is also performed to verify the simulation results. Furthermore, some new designs on the manufacturing of the module strip, such as reducing the density of module or cutting grooves on the PCB, adding extra pins on the carrier, are proposed and compared with the currently used one. The results show that pin carrier is an effective way to reduce the warpage. The more pins on the carrier, the more efficient in reducing the warpage. Decreasing the unit density on the PCB or cutting grooves in the PCB are also ways to reduce the warpage. The less units on a single PCB sheet, the smaller the warpage. The most effective method to reduce strip warpage is to add a central pin on the PCB which can help control the maximum warpage to be within 50 mum. View full abstract»

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  • Electrical conducting behavior of hybrid nanocomposites containing carbon nanotubes and carbon black

    Publication Year: 2007 , Page(s): 1 - 4
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    Nanocomposites reinforced with hybrid fillers of carbon nanotube (CNT) and carbon black (CB) were developed, aiming at enhancing the electrical conductivity of the composites with balanced mechanical properties while lowing the cost of the final product. Epoxy-based nanocomposites were successfully prepared with varying combinations of CNT and CB as conductive fillers and their electrical and mechanical properties were evaluated. It was shown that adding CB in CNT composites can enhance the electrical conductivity of the composites: a low percolation threshold was achieved with 0.20 wt% CNTs and 0.20 wt% of CB. CB enhanced the ductility of the nanocomposites, confirming the synergic effect of CB as an effective multi-functional filler. Flexural modulus and strength were remained at around 3.30 GPa and 110 MPa, respectively, between the composites containing CNT only and those filled with hybrid fillers. The implications of the findings are discussed regarding practical applications of the composites as the thermal interface material for electronics packaging. View full abstract»

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  • Low temperature processing for integrated magnetics

    Publication Year: 2007 , Page(s): 1 - 22
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    First Page of the Article
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  • On the study of MOSFET micro-sensors for electronic packaging

    Publication Year: 2007 , Page(s): 1 - 5
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    The purpose of this paper is to study the MOSFET stress sensor behaviors and to develop the related measurement methodology. With the newly developed technology, the piezoresistance coefficients of the MOSFET were extracted, and the strain and temperature effect induced MOSFET characteristics were obtained. The results of this study can be used to adjust the chip structure in a packaging so that the optimal packaging technology and material can be chosen, and accuracies of the numerical analysis can be verified through experimental data with the new technology studied in this paper. View full abstract»

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  • Thermal simulation and power map modeling sensitivity study for chipset silicon

    Publication Year: 2007 , Page(s): 1 - 5
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    This paper describes the thermal characterization and power map methodology on chipset silicon die. The on-die power map affects the overall thermal gradient and heat spreading effect from the die to the package top, which in turns drives the cooling requirements needed to meet package cooling target. This paper demonstrates the power-thermal simulation with different power map resolution and examines its effects on the hot spot on the die. View full abstract»

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  • Enabling recipe automation for non SECS/GEM semiconductor assembly machines.

    Publication Year: 2007 , Page(s): 1 - 7
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    In today's semiconductor manufacturing, recipe is a very important portion of the machine system. With that in mind, there is a huge demand to enable recipe automation. Recipe automation here basically covers the download and upload of a process program. The download refers to downloading from the host to the machine, while the upload is referring to transfer of process program from the machine to the host. For a non-SECS/GEM machine (i.e., one that does not support communication to the host) this will be a challenge. The main objective of performing recipe automation is to ensure that the correct recipe is being used during the bonding process. With this, we can eliminate mis-processing that is due to loading the wrong recipe. View full abstract»

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  • Effects of aging and underfills on mechanical-drop tests of SnAgCu PBGA (plastic ball grid array) packages on ImAg PCB (printed circuit board)

    Publication Year: 2007 , Page(s): 1 - 8
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    The effects of aging and underfills on the drop test of lead- free (SnAgCu or SAC) PBGA packages on ImAg (immersion silver) PCB are investigated. Two different underfills are studied. These underfills are dispensed on the PCB to fill the gaps between the BT (bismaleimide triazene) substrate of the PBGA, the Sn3wt%Ag0.5wt%Cu solder balls and paste and the PCB. In addition, two more sets of samples (without underfull) are tested (one is with SAC solder balls and paste and the other is with Sn37wt%Pb solder balls and paste), which serve as controls. The sample size for each of the 4 different sets of samples is 24 and half of them (12) are subjected to temperature aging (125degC for 500 hours). The test condition is based on JESD-B 111 (the acceleration = 2900G and the impact duration = 0.3ms). A strain gauge is used to measure the deformation of the test board during impacts. The true characteristic life, true mean time to failure (MTTF), and true Weibull slope of the PBGA interconnects under certain confidence requirements have also been determined. Failure analysis has been performed and examined on some of the failed samples. The results presented in this study should be useful for understanding the effects of aging and underfills on the lead-free PBGA interconnect reliability under drop conditions. View full abstract»

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  • Electrical and reliability properties of isotropic conductive adhesives (ICAs) on immersion silver printed wiring boards (PWBs)

    Publication Year: 2007 , Page(s): 1 - 4
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    To completely eliminate lead (Pb) from electronics, the printed wiring board (PWB) must also change from hot-air- leveled solder (SnPb) to alternative metallic finishes, such as immersion-silver (Ag), immersion-tin (Sn), electroless nickel (Ni)/immersion-gold (Au) and organic solderability preservative (OSP). Especially, immersion-Ag is one of the leading Pb-free final finish choices for many OEMs in the telecommunications, computer, automotive and consumer electronics industries, because of its excellent properties and reasonable cost. This paper presents the electrical properties of Ag epoxy composite isotropic conductive adhesives (ICAs) materials on Cu-finished and immersion-Ag finished PWBs, as solder replacements for SMT or flip chip technologies. All PWBs were subjected to 85degC/85% relative humidity (RH) aging testing, with junction resistance monitored for comparison of the immersion-Ag board to the Cu-finished board as a control. We expected that the corrosion potential, which is one of main causes to degrade conductivity between ICAs and PWB, should be eliminated by the use of Ag contact pads with the Ag epoxy composite ICAs materials. Not only is the junction resistance of immersion-Ag finished boards lower than that of Cu finished boards, but its junction resistance changes are smaller than those of Cu-finished boards, as expected. View full abstract»

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  • Transmission property of adhesive interconnect for high frequency applications

    Publication Year: 2007 , Page(s): 1 - 6
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    The radio frequency (RF) and high frequency performance of the flip chip interconnects with anisotropic conductive film (ACF) and non-conductive film (NCF) was investigated by measuring the scattering parameters (S-parameters) of the flip chip modules. The effects of two chip materials, Si and gallium arsenide (GaAs), and of the metal pattern gap between the signal line and ground plane in the coplanar waveguide (CPW) on the RF performance of the flip chip module were also investigated. The transmission properties of the GaAs were markedly improved on those of the Si chip, which was not suitable for the measurement of the S-parameters of the flip chip interconnect. Extracted impedance parameters showed that the RF performance of the flip chip interconnect with NCF was slightly better than that of the interconnect with ACF, mainly due to the self inductance of the conductive particle surface and the mutual inductance between the conductive particles in the ACF interconnect. View full abstract»

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  • Determination of LED die strength

    Publication Year: 2007 , Page(s): 1 - 6
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    LED (Light Emitting Diode), converting the electron current into the light through the p-n junction of semiconductor diodes, has recently gained popularity worldwide. The high-power LEDs are found in a number of applications to high-volume consumer markets, such as illumination, signaling, screen backlights, automotives and so on. In these applications, the high-power LED packages would be subjected to mechanical, thermal, and environmental loadings during manufacturing processes and services. The strength of LED dies, cut from wafers, has to be determined for the design need in order to assure good reliability of the packages in manufacturing and service. The objective of this study is to determine high-power LED die strength with size of 1 times 1 times 0.1 mm by point-load test (PLT) and line-load test (LLT) associated with a plate-on-elastic-foundation configuration. The finite element analysis and the related stress formulation are used to correlate the failure force of the tests to die strength. It is found that the good consistency of the strength data (~1.3 GPa) with a minor scatter from both the point- and line-load tests is for the specimens failed on chip surfaces, but not for the ones (-1.2 GPa and -0.6 GPa, respectively) failed on the ground surfaces. The inconsistency of strength data from both tests for failure on ground surfaces is found due to edge chipping, observed by scanning electron microscopy. As a result, it can be confirmed that the LED die strength has been successfully determined by these feasible and reliable test methods. View full abstract»

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  • Characterization of residual strains of the EMC in PBGA during manufacturing and IR solder reflow process

    Publication Year: 2007 , Page(s): 1 - 8
    Cited by:  Papers (1)
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    The coplanarity of the plastic ball grid array (PBGA) packages is one of important issues related to the package assembly and solder ball reliability. This issue would become more severe, when the size of the packages is getting larger and the temperature of solder reflow getting higher (due to the application of lead-free solders). Recently published results indicated that residual strains (mainly involving curing shrinkage strains and stress relaxation) of the epoxy molding compound (EMC) play an important role on the warpage values and shapes of the PBGA packages. But it is still unknown about how these residual strains change during the manufacturing and IR reflow processes. The purpose of this study is to quantify the residual strains of the EMC in the PBGA packages during the aforementioned processes by combining experimental, theoretical and numerical approaches. In the experiments, a full-field shadow moire with a sensitivity of 30 mum/fringe is used for measuring their realtime out-of-plane deformations (warpages), during heating and cooling conditions, of two types of the PBGA specimens (without a silicon chip inside) with the same EMC but different substrates (with Tg=172 and 202degC). The elastic moduli (Es) and coefficients of thermal expansion (CTEs) for the EMC and organic substrates are measured in terms of temperatures by dynamic mechanical analyzer (DMA) and thermal mechanical analyzer (TMA), respectively. Timoshenko's bi-material theory is applied for extracting residual strains of the EMC from shadow moire results. And the finite element method cooperating with those determined residual strains is employed to numerically simulate the thermal-induced deformations of the PBGA specimens, in order to verify mechanics. The full-field warpages of the after-cured specimens from shadow moire were documented before and after post-mold curing, solder reflow and during the temperature cycling (from room temperature to 260degC). The residual strains of the - EMC for the specimens with low-Tg and high-Tg substrate after post-mold curing were found to be 0.059% and 0.134%, respectively, which double those before post-mold curing, and further down to 0.035% and 0.08% after the first thermal cycling. After the first cycling, the residual strains keep almost constant during heating and cooling processes. This phenomenon was also observed at lead-free solder reflow processes. Therefore, the residual strains of the EMC induced by the chemical shrinkage of the EMC curing and possibly mold flow pressure are different between with low-Tg and high-Tg substrates, and they can bechanged during post-mold curing processes and stress relaxations during the first solder reflow. View full abstract»

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  • Planar antennas on flexible substrate for wireless applications

    Publication Year: 2007 , Page(s): 1 - 4
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    Flex-circuits are a reliable alternative to conventional electronic products. It can offer the same advantages of a printed circuit board: repeatability, reliability, and high density. The design of a planar antenna on a flexible substrate can effectively supersede that of an antenna on a FR-4 substrate for more flexible applications on wireless system integration, such as RFID or Bluetooth link as well as in steering microwave beam. View full abstract»

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  • Study of contact degradation in final testing for BGA socket

    Publication Year: 2007 , Page(s): 1 - 6
    Cited by:  Papers (1)
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    BGA socket is most important part in the final testing which selects the good or bad chip of BGA packages. When testing BGA-type packages using a BGA socket, the characteristic contact conditions and mechanisms of surface degradation in a low and stable contact are essential. However, the electrical contact between the pogo pin and the solder ball of the BGA-type package becomes unstable following repeated touchdown operations since particles from the package outline gradually accumulate on the crown tip of pogo pin. The contamination caused by these particles causes the contact resistance to increase. Accordingly, this study develops an experimental procedure for investigating the effect of the particle contamination on the magnitude and stability of the contact resistance. Initially, an experiment is performed to establish the contact resistance between a plated beryllium-copper (BeCu) pin at various number of touchdown. Subsequently, an experiment is conducted to investigate the accumulation of surface particles on the crown tip following multiple touchdowns of the pogo pin with the surface solder ball. The worn-out of crown tip following 6,830 and 36,580 touchdowns, respectively, is examined using a scanning electron microscope (SEM). The experimental results are then integrated to establish a suitable tradeoff between the contact resistance and the number of contacts for the time of socket clean. View full abstract»

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  • MCM placement problem with GASA multi-objective optimization strategy

    Publication Year: 2007 , Page(s): 1 - 7
    Cited by:  Papers (1)
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    Placement of multiple dies on an MCM substrate is a difficult combinatorial task in which multiple criteria need to be considered simultaneously to obtain a true multi-objective optimization. In this paper we described a MCM placement model for the multi-objective optimization problem and solved this model by the simulated annealing SA algorithm and the hybrid optimization strategy GASA (namely the combination of genetic algorithm and simulated annealing) respectively. Our design methodologies consider multi- objective component placement based on thermal reliability, routing length and chip area criteria for multi-chip module. The purpose of the multi-objective optimization placement is to enhance the system performance, reliability and reduce the substrate area by obtaining an optimal cost during multi-chip module placement design phase. For reliability considerations, the design methodology focuses on the placement of the power dissipating chips to achieve uniform thermal distribution. For route-ability consideration, the total wire length minimization is estimated by bounding box approximation method. For substrate area consideration, the area is estimated by minimum area contains all chips. The cost function is formulated by the weight sum calculation. For design flexibility, different weights can be assigned depending on designer's considerations. Various methods including simulated annealing and hybrid generic algorithm are applied to solve the placement solutions. 3-D finite element analysis (FEA) is carried out to assess thermal distribution in MCM substrate. The optimization results of various weighting assignments obtained by different algorithms are compared. In addition, an auto generated optimal placement layout based on the analytical solution is also presented. View full abstract»

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  • Tensile test of notched metal film by means of thermal expansion of plastics

    Publication Year: 2007 , Page(s): 1 - 7
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    Tensile tests of notched thin film of pure titanium were carried out on the stage of a digital microscope. Tensile load was generated by the thermal expansion of a pair of polycarbonate loading plates which sandwiched the specimen. Since the thermal expansion coefficient of polycarbonate is much larger than that of pure titanium, the specimen was elongated with an increase in the temperature and successfully fractured at the end of the tensile test. The plastic deformation of the notched part of the specimen was observed during the test and the stress and strain were evaluated. The obtained stress-strain curves were compared with those obtained by a tensile testing device with a piezoelectric stage at the room temperature and 363 K which approximately corresponds to the maximum temperature of the thermal stress-actuated tensile test. View full abstract»

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  • A nondestructive evaluation system for detecting open failures of micro bump interconnections in 3D-stacked structures

    Publication Year: 2007 , Page(s): 1 - 6
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    A nondestructive evaluation system for detecting delamination between a chip and micro bumps in 3D-stacked structures is indispensable for highly reliable and low-cost manufacturing. In stacked structures, it is hard to inspect the adhesion condition of metallic bumps that connect a lower chip with an upper chip because most of the bumps are invisible. We have, therefore, proposed a new nondestructive evaluation method for detecting delamination between a chip and metallic bumps by measuring the local surface deformation of the chip. We have already validated that the local deformation of thinned chips significantly increases when the defects such as a lack and delamination of bumps occur. In this research, the theoretical limit of the minimum detectable gap of the delamination was analyzed using a finite element method. It was found that 1 mum-thick delamination can be detected. In addition, to improve the accuracy of this evaluation method, noise factors that affect the amplitude of the local surface deformation of a chip were discussed and the noise reduction algorithm was proposed based on the analytical results. For example, the effect of the fluctuation of bump height can be eliminated by analyzing the difference of local deformation between before and after underfill filling. In order to validate the effectiveness of this inspection method for detecting open failures in 3D-stacked structures, we made test area-arrayed 3D-stacked chips and measured the local deformation at a surface of the test chips. It was confirmed that the defects of the bump interconnections could be detected precisely by measuring the change of the amplitude in 3D-stacked structures. Therefore, we concluded that a nondestructive evaluation system for micro bump interconnections in 3D-stacked structures has been established successfully. View full abstract»

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  • Intermetallic compound formation and solder joint reliability of Sn-Ag-Cu solder ball on Cu-Zn substrate

    Publication Year: 2007 , Page(s): 1 - 4
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7350 KB) |  | HTML iconHTML  

    We recently developed Cu-Zn alloy wetting layer for the SAC solder balls to improve the reliability. In this paper, IMC formation and solder joint reliability have been investigated in the solder joint between SAC solder balls and Cu-Zn alloy pads, and Cu pads were also used as a reference. Sn-4.0Ag-0.5 Cu solder balls were used and the substrates were Cu and 80 wt% Cu-20 wt% Zn pads which were defined with solder masks. The SAC solder balls on Cu or Cu-Zn pads were reflowed and the solder bump specimens were aged at 150degC up to 1000 h. The Cu6Sn5 and large Ag3Sn plates in the solder ball were formed at the SAC/Cu interfaces after soldering. The well-known double layer structure of Cu-Sn IMCs (Cu6Sn5 and Cu3Sn) and Kirkendall voids formed in the SAC/Cu interfaces during aging. On the SAC/Cu-Zn interfaces, Cu6Sn5 formed after soldering and thickened with aging. However, Cu3Sn IMC was not formed on SAC/Cu-Zn interfaces after aging. Also, the growth rate of IMCs at the SAC/Cu-Zn interface was much slower than that at the SAC/Cu interface. The ball shear test was conducted after soldering and aging to evaluate solder joint strength. The fracture mainly occurred in the solder and the shear strength value decreased with increasing aging time on both SAC/Cu and SAC/Cu-Zn. The shear strength of SAC solder on Cu substrates was lower than that of SAC solder on Cu-Zn substrates during aging. View full abstract»

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  • Investigation of the thermal performance of high-concentration photovoltaic solar cell package

    Publication Year: 2007 , Page(s): 1 - 6
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6959 KB) |  | HTML iconHTML  

    The demand for energy resources to improve our quality of life continues to increase. However, the prices of Fossil Energy keep going up and the resources are limited. Therefore, more and more reusable energy resources are being developed. The foremost among these reusable energy resources is solar energy. A solar cell, powered by solar energy, uses semiconductors to transform light into electric power. The difference in structure between high- concentration photovoltaic (HCPV) solar cell and traditional solar cell is the usage of concentrated-light module to enhance the optic-electric transition efficiency. In general, under concentrated-light operation condition, the device temperature rises with increasing light concentration ratio. In other words, due to a decrease in open-circuit voltage as a function of increasing temperature, the system output power or energy- conversion efficiency decreases with the increasing temperature of the cell incorporated within the system. Therefore, thermal management has been an important issue for the package of a high-concentration photovoltaic solar cell. In this research, we first established a detailed finite element model of the HCPV solar cell package as a benchmark using ANSYSreg finite element analysis program. The established finite element model can simplify and quickly resolve the thermal management problem of the HCPV solar cell package. We also performed Infrared (IR) thermography measurement experiment in order to validate the finite element model. After validation of the experimental results, we analyzed the variation of thermal performance under different design parameters of the HCPV solar cell package. Based on the simulation results of different design parameters, it can be found that the thickness of the heat sink plate plays important roles in the thermal management of the HCPV solar cell package, which indicates that the thicker the thickness of the aluminum plate, the lower the junction temperatu- re of the HCPV solar cell package. Furthermore, the thermal conductivity of the test board and solder paste has a light effect to reduce junction temperature. The other result shows the capability of a protection gel not only to protect the die surface and wire bond but to also reduce cell temperature under a highly concentrated light condition. View full abstract»

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  • Filling of very fine via holes for three dimensional packaging by using ionized metal plasma sputtering and electroplating

    Publication Year: 2007 , Page(s): 1 - 3
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2190 KB) |  | HTML iconHTML  

    One of the key technologies for developing 3-D Packaging with vertical interconnection is the interlayer metallization using formation and filling of through silicon vias. We deal with filling of via holes with diameters of 5.4-7.5 mum and depths of 47-60 mum using Cu electroplating. Prior to electroplating, the interior regions of the via holes are needed to be coated with Cu layer as a seed layer for the subsequent Cu electroplating process. In this work, Cu thin layers are deposited by using ionized metal plasma (IMP) sputtering. The IMP sputtering enables more conformal deposition of Cu seed layer on the sidewall of the via holes than conventional sputtering. And it is more cost-effective than chemical vapor deposition. Deposition profiles of Cu seed layers inside the via holes are closely examined by measuring X-ray intensity ratios of Cu La to Si Ka as a function of substrate bias power. The via holes coated with Cu seed layers are then filled with Cu electroplating. We study the effects of the deposition profiles of Cu seed layers on the filling of electroplated Cu for the via holes. View full abstract»

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  • Local distribution of residual strain in 3-D stacked flip chips measured by strain sensor chips with 2-μm long piezoresistive gauges

    Publication Year: 2007 , Page(s): 1 - 6
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2836 KB) |  | HTML iconHTML  

    Electronic products such as mobile phones and PCs have been miniaturized continuously and their functions have been improved drastically. So far, the electronic interconnection between a chip and a substrate has been wire bonding, but it has started to be changed to flip chip interconnection structures because signal delay clearly appears due to the increase of the resistance caused by the thinning of the wire. Area-arrayed tiny metallic bumps such as Cu or solder are applied to the flip chip structure and they are surrounded by insulating material (underfill) for assuring the reliability of the interconnection. Since the total thickness of the stacked structure is strictly limited for the mobile application, in particular, the thickness of a chip has been thinned to less than 50 mum to minimize the total thickness of the modules or packages. However, a distribution of local thermal strain appears clearly on the surface of the stacked silicon chip mounted using flip chip technology when the thickness of a silicon chip becomes thinner than 200 mum. This local strain distribution sometimes deteriorates the electronic performance of devices and thus, degrades their reliability. Therefore, the quantitative evaluation of the residual strain in flip chip structures has become very important. To evaluate the local stress/strain distribution quantitatively, we have successfully developed strain sensor chips with 2-mum long piezoresistive gauges that consist of diffused resistors embedded in single-crystalline silicon. The local distribution of the residual thermal strain in a silicon chip caused by the area-arrayed small bumps and the material properties of underfill material can be measured using the sensor chips. The distributions of residual strain were measured in the active layers on the stacked chip surfaces mounted by flip chip technology. The measured amplitude of the distribution of the local stress in one chip reached about 200 MPa. In addition, it was confirmed t- hat the stress distribution in the tacked chips varied drastically depending on the bump alignment. View full abstract»

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  • Accuracy improvement of full-field displacement measurement using digital image correlation for images obtained with a laser scanning confocal microscope

    Publication Year: 2007 , Page(s): 1 - 5
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6555 KB) |  | HTML iconHTML  

    A method for image correction is proposed for digital image correlation in conjunction with a laser scanning confocal microscope (LSCM). The scan lines of an LSCM have sub-pixel error in their position in the scanning direction (drift distortion). Drift distortion decreases the accuracy of the displacement measured using the DIC method. The correction method proposed here removes both drift distortion and spatial distortion. Drift distortion is removed using a pair of images, each of which has a different scanning direction. Spatial distortion removal is performed using a methodology that employs a series of in-plane rigid body motions and a generated distortion map. Numerical simulations demonstrated that these correction procedures can successfully detect drift distortion. The standard deviation (SD) of the obtained detection error for artificial noise with sub-pixel line-shift was 0.004 pixels. Experimental results involving rigid body motion indicate that, after the correction of drift and spatial distortions, (i) the standard deviation of the measured displacements was 0.03 pixels, and (ii) the measured displacement fields are unbiased and agree closely with those obtained using an optical microscope. The proposed correction method effectively removes the distortions of obtained images and improves the accuracy of the digital image correlation method using an LSCM. View full abstract»

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