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Semiconductor Manufacturing, 2006. ISSM 2006. IEEE International Symposium on

Date 25-27 Sept. 2006

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  • [Front cover]

    Publication Year: 2006, Page(s): C1
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  • The Thirteenth International Symposium on Semiconductor Manufacturing

    Publication Year: 2006, Page(s): i
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  • [Copyright notice]

    Publication Year: 2006, Page(s): ii
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  • Welcome to ISSM 2006

    Publication Year: 2006, Page(s): iii
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  • Message from ISSM 2006 Executive Committee Chair

    Publication Year: 2006, Page(s): iv
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  • Message from ISSM 2006 Japan Program Committee Chair

    Publication Year: 2006, Page(s): v
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  • ISSM 2006 Committee

    Publication Year: 2006, Page(s):vi - viii
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  • ISSM 2006 Sponsoring Organizations

    Publication Year: 2006
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  • ISSM 2006 Sponsorship Acknowledgement

    Publication Year: 2006
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  • ISSM 2006 Program At a Glance

    Publication Year: 2006, Page(s): xi
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  • Keynote Speeches

    Publication Year: 2006, Page(s): xii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (505 KB) | HTML iconHTML

    Provides an abstract for each of the keynote presentations and a brief professional biography of each presenter. View full abstract»

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  • ISSM 2006 Program Schedule

    Publication Year: 2006, Page(s):xiii - xxii
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  • Conquering Process Variability: A Key Enabler for Profitable Manufacturing in Advanced Technology Nodes

    Publication Year: 2006, Page(s):xxiii - xxxii
    Cited by:  Papers (10)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (7238 KB) | HTML iconHTML

    Achieving the required time to market with economically acceptable yield levels and maintaining them in volume production has become a very challenging task in the most advanced technology nodes. One of the primary reasons is the relative increase in process variability in each generation. This paper will describe a comprehensive study of the main sources of variability and their effects on active... View full abstract»

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  • Collaboration in the 21st Century: Driving-Innovation and Differentiation

    Publication Year: 2006, Page(s):xxxiii - xlviii
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (6738 KB) | HTML iconHTML

    The article consists of a Powerpoint presentation on collaboration in the 21st Century. The areas discussed include SOC design; IC scaling technology; cost escalation; time-to-market; supply chain complexity; collaboration; innovation management; intellectual property; globalisation; semiconductor industry; interdependent model; common platform value proposition; multifab concept and ec... View full abstract»

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  • The CASMAT Business Model for Semiconductor Materials

    Publication Year: 2006, Page(s):xlix - li
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (685 KB) | HTML iconHTML

    The consortium for advanced semiconductor materials and related technologies (CASMAT) was established in March 2003 to enable innovating material development efficiency and to open a market for new materials. Major Japanese manufacturers of semiconductor materials sponsor the consortium to strengthen their competitiveness in the global market. The member companies develop the materials themselves,... View full abstract»

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  • Toshiba's Strategy in Semiconductor Business and Production Technology

    Publication Year: 2006, Page(s): liii
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (410 KB)

    First Page of the Article
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  • Future Lithography Challenges

    Publication Year: 2006, Page(s):lv - lx
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (3802 KB) | HTML iconHTML

    For the past 25 years, the resolution and productivity of lithography exposure tools have continuously improved. The latest exposure tools have adopted immersion technology with ArF excimer lasers for the production of half pitch (HP) 55 nm to 45 nm patterns and beyond. For HP 32 nm, EUVL is the main candidate. The author reports the status of development of EUV tools and future lithography challe... View full abstract»

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  • The Strategy for Manufacturing Technology Advancement in Memory

    Publication Year: 2006, Page(s):lxi - lxiii
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (433 KB)

    Semiconductor industry, evolved around PC-oriented products, will grow more rapidly as its application diversifies to mobile devices, digital consumer electronics, etc.. The segmentation of usage, multiplication of function, and minimization of products allow the industry to expand more dynamically. Samsung Electronics stands in the very center of this change. Last year's introduction of 16-gigabi... View full abstract»

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  • [Breaker page]

    Publication Year: 2006, Page(s): 1
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  • Watermark induced High Density Via failures in sub micron CMOS fabrication

    Publication Year: 2006, Page(s):3 - 6
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1558 KB) | HTML iconHTML

    High via resistance was detected in the high density via structure in our 0.15 mum BEOL (Back-End-Of-Line) yield monitoring test vehicle. A localized insulating layer was found on top of plug in test vehicle causing high via resistance. The failure was attributed to watermark induced contaminants on top of the W plug. It was shown that the failure could be avoided by eliminating watermark formatio... View full abstract»

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  • In Situ Particle Monitors: The Next Level of Yield Control for Critical Processes

    Publication Year: 2006, Page(s):7 - 10
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (2632 KB) | HTML iconHTML

    In situ particle monitors (ISPM) have been used in the semiconductor industry for many years to monitor chamber condition before and after preventative maintenance. New improvements in particle detection technology combined with novel methods to remove particles from the chamber are proving that ISPM technology is a key component in the fight to improve product yields. View full abstract»

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  • Voltage Contrast Enhancement for Gate Leak Failure Detected by Electron Beam Inspection

    Publication Year: 2006, Page(s):11 - 14
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (2551 KB) | HTML iconHTML

    We studied the VC (voltage contrast) enhancement technique of the FA (failure analysis) tool. We found a gate leak VC dependency on the relative angle between the beam scan direction and gate electrode direction. A simplified RC model can explain this phenomenon qualitatively. With the help of this VC enhancement technique of the FA tool, we could tune the EBI recipe in appropriate sensitivity. As... View full abstract»

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  • Method of Minimizing Inspection Cost by Making Use of Programmed Defect Array

    Publication Year: 2006, Page(s):15 - 17
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1899 KB) | HTML iconHTML

    In order to set up the well-balanced defect inspection recipe on right inspection tool, it is important to evaluate the tradeoff between inspection throughput and sensitivity. The sensitivity of defect inspection is difficult to define because it depends not only on defect size but also the shape and material of defects. This paper describes a methodology to quantitatively evaluate the sensitivity... View full abstract»

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  • Failure Mode Detection and Process Optimization for 65 nm CMOS Technology

    Publication Year: 2006, Page(s):18 - 21
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1713 KB) | HTML iconHTML

    Short loop test flows have been commonly used in back end of line (BEOL) interconnect process development to speed up learning rates and improve yields. This paper presents case studies on the expanded use of short loop test chips to the shallow trench isolation (STI), gate and pre- metal dielectric (PMD)Z contact loops of a 65 nm process technology in addition to the BEOL. These test chips have b... View full abstract»

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  • Electrical Defect Density Test Structures for DFM in the Sub-wavelength Lithography Regime with Copper Metallization

    Publication Year: 2006, Page(s):22 - 24
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1733 KB) | HTML iconHTML

    Serpent/comb test structures are standard electrical defect monitors for semiconductor interconnect processes. Traditionally, these test structures are drawn as straight lines, based on the assumption that defects are random and independent of geometry. However, with lithography now performed in the sub-wavelength regime, critical dimensions are not always printed as drawn, depending on the surrou... View full abstract»

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