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Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on

Date 17-19 March 2008

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  • [Front cover]

    Publication Year: 2008 , Page(s): c1
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  • [Title page i]

    Publication Year: 2008
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  • [Title page iii]

    Publication Year: 2008 , Page(s): iii
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  • [Copyright notice]

    Publication Year: 2008 , Page(s): iv
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  • Table of contents

    Publication Year: 2008 , Page(s): v - xviii
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  • Welcome Notes

    Publication Year: 2008 , Page(s): xix - xx
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  • Organizing Committee / Best Paper

    Publication Year: 2008
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  • Technical Subcommittee Lists

    Publication Year: 2008 , Page(s): xxii - xxv
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  • Steering/Advisory Committee

    Publication Year: 2008 , Page(s): xxvi
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  • Conference at a glance

    Publication Year: 2008 , Page(s): xxvii - xxviii
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  • Tutorial 1: The Promise of High-k/Metal Gates-From Electronic Transport Phenomena to Emerging Device/Circuit Applications

    Publication Year: 2008 , Page(s): 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (181 KB) |  | HTML iconHTML  

    Summary form only given. Recent advancements of gate stack engineering have enabled the introduction of high-k/metal gates into mainstream CMOS device applications for 45 nm and beyond technology space. In this talk, we take a critical look back into the key steps which made this possible with primary focus on transport phenomena in transistors in presence of high-k/metal gates. Against this backdrop, the interaction of high-k/metal gates with end of roadmap devices would be thoroughly explored. High-k/metal gates have interesting ramifications in the circuit space-from NBTI (negative bias temperature instability) to high-field mobility, the high-k gate induced physical phenomena and their impact on device and circuit performance and reliability would be discussed. To conclude, this talk would also conjecture on the continued scalability of high-k gate stacks for futuristic CMOS device architectures. View full abstract»

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  • Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies

    Publication Year: 2008 , Page(s): 4
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    Summary form only given. In order to continue CMOS scaling towards the physical limit, care must be taken to account for each obstacle that is currently impeding our progress. Increased power consumption and faster current transients have deteriorated on-chip power supply integrity. Long term reliability issues such as negative bias temperature instability (NBTI) have become serious problems degrading the performance and yield of high performance systems. This talk will focus on circuit design techniques to deal with power supply noise and aging issues in sub-32nm technologies. First, modeling and design techniques are presented for reliable on-chip power supply delivery. Next, an overview of several reliability mechanisms will be given followed by some recent developments on monitoring techniques to accurately measure and model the circuit aging impact. View full abstract»

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  • Tutorial 3: Process Technology Development and New Design Opportunities in 3D Integration Technology

    Publication Year: 2008 , Page(s): 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (174 KB) |  | HTML iconHTML  

    3D integration offers inter-strata interconnect with high connectivity density, low parasitics, and shorter lengths. This bring advantages in increased interconnect bandwidth, reduced interconnect latency and reduced power consumption in comparison with individual packaged chips on a board or packages with wire bonded stacked die. 3D integration can compete with, or even surpass, SoC (system on a chip) integration in terms of interconnect performance while allowing for differentiated process technologies for the various strata. View full abstract»

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  • Tutorial 4: Robust System Design in Scaled CMOS

    Publication Year: 2008 , Page(s): 6
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    Summary form only given. The aim of this paper is to develop enabling technologies and tools spanning multiple abstraction levels to design globally optimized robust systems without incurring the high cost of traditional redundancy. An architecture-aware circuit design technique corrects radiation-induced soft errors in latches, flip-flops, and combinational logic at extremely low-cost compared to redundancy techniques. A new design technique, distinct from error detection, predicts failures before they actually create errors in system data and states. Circuit failure prediction is ideal for reliability mechanisms such as transistor aging and early-life failures, and can enable close to best-case design by minimizing traditional worst-case speed guardbands. View full abstract»

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  • Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve?

    Publication Year: 2008 , Page(s): 7
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (171 KB) |  | HTML iconHTML  

    Summary form only given. Choosing data storage arrays for a microprocessor design is driven by a delicate balance of technology readiness, circuit-level design factors, and system-level performance, power, and scaling implications. Recently, CMOS technologists have warned of the "end of scaling," and cite particular concern for six-transistor SRAM. This is a startling forecast, since easily 50% of microprocessor silicon area is commonly occupied by SRAM caches. A particularly long-standing debate has surrounded one dense, resilient, on-chip storage alternative: embedded DRAM. This tutorial will provide background on eDRAM, and show how its circuit and technology properties translate to metrics used to make decisions at the chip and architecture levels: cache capacity, cache access latency, and cache distance from the CPU. View full abstract»

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  • Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM)

    Publication Year: 2008 , Page(s): 8 - 9
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (181 KB) |  | HTML iconHTML  

    Summary form only given. This part of the tutorial will discuss in detail the manufacturing challenges in nanoscale VLSI and consequent design for manufacturability (DFM) approaches by taking a holistic approach in analyzing and addressing different process variability effects. We review the dominant process variations in semiconductor manufacturing process that affect the design yield, show their impact on layout quality, and present currently practiced DFM techniques to mitigate the effect of these variations. We also discuss various manufacturing-aware physical and circuit design methodologies and techniques for parametric yield improvement. This includes correct-by-construction methodologies such as Restricted Design Rules (RDRs) as well as manufacturing aware design approaches. In addition, we will briefly mention some of the many accepted and possible mitigation techniques in design post processing (after tape-out) and will introduce the concept of manufacturing for design (MFD) through design-intent processing. View full abstract»

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  • Plenary Speech 1P1: Shrinking time-to-market through global value chain integration

    Publication Year: 2008 , Page(s): 15
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB) |  | HTML iconHTML  

    Summary form only given. The product development challenges for high-tech companies are even greater than most industries, thanks in large part to their dependence on an increasingly distributed and complex global value chain and extreme pressure to deliver innovation to market quicker than their fierce competition.That chain of frequently independent companies collaborating on these shrinking project timeline stretches from product conception to chip design, product development, production/assembly, testing, packaging, and delivery. Central to addressing these challenges are solutions and interoperable IT enterprise architectures that can streamline this innovation pipeline. In this presentation the author discusses the opportunities to shrink product time-to-market by more quickly, efficiently, and securely collaborating and integrating with product development value chain partners. View full abstract»

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  • Plenary Speech 1P2: Bounding the Endless Verification Loop

    Publication Year: 2008 , Page(s): 16 - 17
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    Summary form only given. Although more and more engineering resources are being focused on verification, most of the effort is expended on re-simulating what has already been simulated. And once the effort is through, only 20% of the state space has been verified, at best. Verification today is a frustrating, open-loop process that often doesn't end even after the integrated circuit ships. In response, the whole verification methodology infrastructure is undergoing major changes - from adoption of assertion-based verification, coverage-driven verification, to new approaches in test bench generation/optimization, integrated hardware acceleration and more. In this session, Robert Hum will explore these and other new solutions and innovations in functional verification technology,and discuss the impact of these changes on the EDA industry. View full abstract»

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  • A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS

    Publication Year: 2008 , Page(s): 23 - 29
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB) |  | HTML iconHTML  

    An eight megabit rad hard SRAM, implemented in 130 nm CMOS technology, uses stacked capacitors within the memory cell for robustness, supply power gating and internally developed array power supplies to achieve very low soft error rates and standby current consumption under 600 nA. View full abstract»

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  • Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation

    Publication Year: 2008 , Page(s): 30 - 34
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB) |  | HTML iconHTML  

    We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90 nm 26 kb SRAM module is reduced from 550 mV to 220 mV. A novel error-tolerant architecture further reduces the minimum static-error-free VDD to 155 mV. With a 100 mV noise margin, a 255 mV standby VDD effectively reduces the SRAM leakage power by 98% compared to the typical standby at 1 V VDD. View full abstract»

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  • Error Protected Data Bus Inversion Using Standard DRAM Components

    Publication Year: 2008 , Page(s): 35 - 42
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (548 KB) |  | HTML iconHTML  

    Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This is either unrealistic or impractical in many industrial situations. In this paper, we propose an architecture which implements classic low power encoding but uses industry standard DRAMs. Moreover, the low power encoding is combined with error-protection in order to extend the application to noisy channels or to the presence of soft and hard failures in the memory. Parallelism between the two encoding processes avoids any latency adder. Our experimental results, based on current consumption measurements of DDR2 DRAM components in mass production, show savings up to 31% on the I/O power and 6% on the total memory energy of a single channel memory system of 4 GB at practically no cost. View full abstract»

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  • Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects

    Publication Year: 2008 , Page(s): 43 - 46
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (365 KB) |  | HTML iconHTML  

    Process variations can have a significant impact on both device and interconnect performance in deep sub-micron (DSM) technology. In this paper, initially authors discuss the effects of process parameter variations on bus-encoding schemes for delay minimization in VLSI interconnects. Later, process variation aware bus-coding scheme is proposed to reduce delay in interconnects. It is shown that if process variability is taken into consideration, effective capacitance (Ceff) of the bus lines varies because of which the amount of delay that each crosstalk class causes is going to vary. SPICE simulations have been carried out for interconnect lines of different dimensions at different technology nodes (180, 130, 90 and 65 nm) to find out the effect of process variation on the effective capacitance of bus lines and to evaluate the percentage delay reduction due to proposed coding scheme. View full abstract»

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  • Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering

    Publication Year: 2008 , Page(s): 47 - 52
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB) |  | HTML iconHTML  

    This paper presents a method for speeding-up ASICs by transistor reordering. The proposed method can be applied to a variety of logic styles and transistor topologies. The rationale of the obtained gains is explained through logical effort concepts. When applied to circuits based on 4-input networks, which is the case of many structured-ASIC or FPGA technologies, significant performance gains are obtained at a small area expense. This observation points out that our method can be of special interest when migrating FPGAs to ASICs. The logical effort effects on networks derived from BDDs illustrated in this paper can be exploited in a much broader range of designs. View full abstract»

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  • Fast and Accurate Waveform Analysis with Current Source Models

    Publication Year: 2008 , Page(s): 53 - 56
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (940 KB) |  | HTML iconHTML  

    Recently current source models (CSMs) have become popular for use in standard cell characterization and static timing analysis. However, there has not been any detailed study of what aspects of the gate behavior should be modeled for sufficient accuracy, and there have been no results reported incorporating a CSM into a timing analysis flow with reasonable runtime. This paper addresses these limitations by investigating complexity/accuracy tradeoffs in CSMs. We then present a novel technique to perform fast, accurate waveform analysis using CSMs. STA results on benchmark circuits show significantly reduced errors compared to a traditional Thevenin-based flow. In terms of mu+sigma percentile, we gain by 20-150 % in slew through this approach. View full abstract»

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  • An Efficient Method for Fast Delay and SI Calculation Using Current Source Models

    Publication Year: 2008 , Page(s): 57 - 61
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB) |  | HTML iconHTML  

    Current source models are the methods of choice for gate-level delay and SI calculation in Deep Sub Micron regime. To fully utilize the information provided by the current source models, numerical integration is often applied to solve stage-based transient simulation that calculates delay, slew, or noise bumps. However, this is computationally expensive. In this paper, we present a fast and robust algorithm for delay and signal integrity (SI) calculation using current source models. By applying diagonalization and Sherman-Morrison formula together with a one-step Newton-Raphson method, the transient simulation cost of a stage with a single driver can be reduced from O(kmn3) to O(kn) with a small runtime overhead, where k is the number of time step, m is the average number of Newton-Raphson steps, and n is the size of matrices of the Reduced Order Model(ROM) of the parasitic network. The proposed method works perfectly with the popular implicit integration methods such as the Trapezoidal and Backward Euler method. View full abstract»

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