9th International Symposium on Quality Electronic Design (isqed 2008)

17-19 March 2008

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  • [Front cover]

    Publication Year: 2008, Page(s): c1
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  • [Title page i]

    Publication Year: 2008
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  • [Title page iii]

    Publication Year: 2008, Page(s): iii
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  • [Copyright notice]

    Publication Year: 2008, Page(s): iv
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  • Table of contents

    Publication Year: 2008, Page(s):v - xviii
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  • Welcome Notes

    Publication Year: 2008, Page(s):xix - xx
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  • Organizing Committee / Best Paper

    Publication Year: 2008
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  • Technical Subcommittee Lists

    Publication Year: 2008, Page(s):xxii - xxv
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  • Steering/Advisory Committee

    Publication Year: 2008, Page(s): xxvi
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  • Conference at a glance

    Publication Year: 2008, Page(s):xxvii - xxviii
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  • Tutorial 1: The Promise of High-k/Metal Gates-From Electronic Transport Phenomena to Emerging Device/Circuit Applications

    Publication Year: 2008, Page(s): 3
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (181 KB) | HTML iconHTML

    Summary form only given. Recent advancements of gate stack engineering have enabled the introduction of high-k/metal gates into mainstream CMOS device applications for 45 nm and beyond technology space. In this talk, we take a critical look back into the key steps which made this possible with primary focus on transport phenomena in transistors in presence of high-k/metal gates. Against this backd... View full abstract»

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  • Tutorial 2: Low Voltage Circuit Design Techniques for Sub-32nm Technologies

    Publication Year: 2008, Page(s): 4
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (171 KB) | HTML iconHTML

    Summary form only given. In order to continue CMOS scaling towards the physical limit, care must be taken to account for each obstacle that is currently impeding our progress. Increased power consumption and faster current transients have deteriorated on-chip power supply integrity. Long term reliability issues such as negative bias temperature instability (NBTI) have become serious problems degra... View full abstract»

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  • Tutorial 3: Process Technology Development and New Design Opportunities in 3D Integration Technology

    Publication Year: 2008, Page(s): 5
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (174 KB) | HTML iconHTML

    3D integration offers inter-strata interconnect with high connectivity density, low parasitics, and shorter lengths. This bring advantages in increased interconnect bandwidth, reduced interconnect latency and reduced power consumption in comparison with individual packaged chips on a board or packages with wire bonded stacked die. 3D integration can compete with, or even surpass, SoC (system on a ... View full abstract»

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  • Tutorial 4: Robust System Design in Scaled CMOS

    Publication Year: 2008, Page(s): 6
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (184 KB) | HTML iconHTML

    Summary form only given. The aim of this paper is to develop enabling technologies and tools spanning multiple abstraction levels to design globally optimized robust systems without incurring the high cost of traditional redundancy. An architecture-aware circuit design technique corrects radiation-induced soft errors in latches, flip-flops, and combinational logic at extremely low-cost compared to... View full abstract»

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  • Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve?

    Publication Year: 2008, Page(s): 7
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (171 KB) | HTML iconHTML

    Summary form only given. Choosing data storage arrays for a microprocessor design is driven by a delicate balance of technology readiness, circuit-level design factors, and system-level performance, power, and scaling implications. Recently, CMOS technologists have warned of the "end of scaling," and cite particular concern for six-transistor SRAM. This is a startling forecast, since easily 50% of... View full abstract»

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  • Tutorial 6: Enhancing Yield through Design for Manufacturability (DFM)

    Publication Year: 2008, Page(s):8 - 9
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (181 KB) | HTML iconHTML

    Summary form only given. This part of the tutorial will discuss in detail the manufacturing challenges in nanoscale VLSI and consequent design for manufacturability (DFM) approaches by taking a holistic approach in analyzing and addressing different process variability effects. We review the dominant process variations in semiconductor manufacturing process that affect the design yield, show their... View full abstract»

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  • Plenary Speech 1P1: Shrinking time-to-market through global value chain integration

    Publication Year: 2008, Page(s): 15
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB) | HTML iconHTML

    Summary form only given. The product development challenges for high-tech companies are even greater than most industries, thanks in large part to their dependence on an increasingly distributed and complex global value chain and extreme pressure to deliver innovation to market quicker than their fierce competition.That chain of frequently independent companies collaborating on these shrinking pro... View full abstract»

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  • Plenary Speech 1P2: Bounding the Endless Verification Loop

    Publication Year: 2008, Page(s):16 - 17
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (149 KB) | HTML iconHTML

    Summary form only given. Although more and more engineering resources are being focused on verification, most of the effort is expended on re-simulating what has already been simulated. And once the effort is through, only 20% of the state space has been verified, at best. Verification today is a frustrating, open-loop process that often doesn't end even after the integrated circuit ships. In resp... View full abstract»

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  • A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS

    Publication Year: 2008, Page(s):23 - 29
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB) | HTML iconHTML

    An eight megabit rad hard SRAM, implemented in 130 nm CMOS technology, uses stacked capacitors within the memory cell for robustness, supply power gating and internally developed array power supplies to achieve very low soft error rates and standby current consumption under 600 nA. View full abstract»

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  • Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation

    Publication Year: 2008, Page(s):30 - 34
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB) | HTML iconHTML

    We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90 nm 26 kb SRAM module is reduced from 550 mV to 220 mV. A novel error-tolerant architecture further reduces the minimum static-error-free VDD to 155 mV. With a 100 mV noise margin, a 255 mV standby VDD effecti... View full abstract»

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  • Error Protected Data Bus Inversion Using Standard DRAM Components

    Publication Year: 2008, Page(s):35 - 42
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB) | HTML iconHTML

    Off-chip communication consumes a significant part of main memory system power. Existing solutions imply the use of specialized memories or assume error free environments. This is either unrealistic or impractical in many industrial situations. In this paper, we propose an architecture which implements classic low power encoding but uses industry standard DRAMs. Moreover, the low power encoding is... View full abstract»

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  • Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects

    Publication Year: 2008, Page(s):43 - 46
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (365 KB) | HTML iconHTML

    Process variations can have a significant impact on both device and interconnect performance in deep sub-micron (DSM) technology. In this paper, initially authors discuss the effects of process parameter variations on bus-encoding schemes for delay minimization in VLSI interconnects. Later, process variation aware bus-coding scheme is proposed to reduce delay in interconnects. It is shown that if ... View full abstract»

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  • Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering

    Publication Year: 2008, Page(s):47 - 52
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB) | HTML iconHTML

    This paper presents a method for speeding-up ASICs by transistor reordering. The proposed method can be applied to a variety of logic styles and transistor topologies. The rationale of the obtained gains is explained through logical effort concepts. When applied to circuits based on 4-input networks, which is the case of many structured-ASIC or FPGA technologies, significant performance gains are ... View full abstract»

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  • Fast and Accurate Waveform Analysis with Current Source Models

    Publication Year: 2008, Page(s):53 - 56
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (940 KB) | HTML iconHTML

    Recently current source models (CSMs) have become popular for use in standard cell characterization and static timing analysis. However, there has not been any detailed study of what aspects of the gate behavior should be modeled for sufficient accuracy, and there have been no results reported incorporating a CSM into a timing analysis flow with reasonable runtime. This paper addresses these limit... View full abstract»

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  • An Efficient Method for Fast Delay and SI Calculation Using Current Source Models

    Publication Year: 2008, Page(s):57 - 61
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB) | HTML iconHTML

    Current source models are the methods of choice for gate-level delay and SI calculation in Deep Sub Micron regime. To fully utilize the information provided by the current source models, numerical integration is often applied to solve stage-based transient simulation that calculates delay, slew, or noise bumps. However, this is computationally expensive. In this paper, we present a fast and robust... View full abstract»

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