Date 19-20 Nov. 2007
Filter Results
Displaying Results 1 - 25 of 55
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Performance analysis of BMC and Decision Units in the differential analog Viterbi decoder
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PDF (813 KB)
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Surface charge detection probe
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PDF (672 KB)
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Power optimized partial product reduction interconnect ordering in parallel multipliers
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PDF (630 KB)
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A low-voltage fully differential constant signal behavior rail-to-rail input stage in 0.12μm CMOS
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PDF (1803 KB)
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LMS-based identification and compensation of timing mismatches in a two-channel time-interleaved analog-to-digital converter
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PDF (833 KB)
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Design of A 7-bit, 200MS/s, 2mW pipelined ADC with switched open-loop amplifiers in a 65nm CMOS technology
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PDF (642 KB)
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Sizing of MOS device in LC-tank oscillators
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PDF (979 KB)
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An 8-bit 10 kS/s 0.18 μm CMOS SAR ADC for RFID applications with sensing capabilities
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PDF (677 KB)
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