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Proceedings of Eighth International Application Specific Integrated Circuits Conference

18-22 Sept. 1995

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  • Proceedings of Eighth International Application Specific Integrated Circuits Conference

    Publication Year: 1995
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    Freely Available from IEEE
  • From real-time emulation to ASIC integration for image processing applications

    Publication Year: 1995, Page(s):31 - 34
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (464 KB)

    A methodology for deriving image processing ASICs from the results of their real-time emulation on the Data-Flow Functional Computer is presented. The aim of the method is to reduce the time and effort required for synthesizing and validating ASICs after emulation. This is achieved by optimizing the architecture validated on the emulator and integrating the optimized resources. The results of the ... View full abstract»

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  • Conference Author Index

    Publication Year: 1995, Page(s):421 - 422
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    Freely Available from IEEE
  • Simultaneous switching noise estimation for ASICs

    Publication Year: 1995, Page(s):7 - 10
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB)

    Simultaneous switching noise (SSN) on power supply lines is caused by the switching current flowing through parasitic inductances at the chip-package-pin interface. A new formulation for SSN in CMOS circuits that includes the velocity saturation effects seen in the short-channel MOSFETs is derived. The effect of skewing output voltage switching among different drivers on SSN is studied. SSN of ASI... View full abstract»

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  • Deration of power dissipated in ASICs with temperature, process, and voltage variations

    Publication Year: 1995, Page(s):3 - 6
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    This paper presents a method to accurately derate power dissipated in ICs as temperature, process, and voltage are varied from the baseline conditions. Our cell-based power consumption model accounts for the waveform slope effects at the input of a gate, its output load, and logical state-dependencies, in terms of pre-characterized power coefficients. We further generalize this model to specify th... View full abstract»

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  • On the complexity of bridging fault simulation techniques for CMOS integrated circuits

    Publication Year: 1995, Page(s):160 - 163
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    Accepted integrated circuit verification techniques involve stuck-at fault simulation. However, it has been shown that the majority of actual physical faults in the faulty integrated circuit are bridging faults. For this reason, the interest in bridging fault simulation techniques has increased. One characteristic with bridging faults is that the bridging fault may have electrical as well as logic... View full abstract»

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  • VHDL and silicon compiler experience in the advanced processor interface unit ASIC design

    Publication Year: 1995, Page(s):329 - 332
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    This paper summarizes the process of designing an advanced processor interface unit (APIU) ASIC using VHDL simulation, synthesis, and silicon compilation. Problems and areas for improvements in the interface between different CAD tool environments are addressed. VHDL entity and hierarchy partition guidelines are discussed with examples View full abstract»

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  • Re-engineering ASIC design with LPGAs

    Publication Year: 1995, Page(s):60 - 63
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    The availability of Laser Programmable Gate-Arrays (LPGAs) of over 100k gates which can be economically produced within a few hours simplifies considerably the design cycle and shortens the time-to-market of systems incorporating gate arrays. The technological background and architecture of LPGAs, and the methodology of transfer from design to volume production are described View full abstract»

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  • Reconfigural content addressable memory for ASIC module compiler

    Publication Year: 1995, Page(s):374 - 377
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    This paper discusses the content addressable memory (CAM) architecture for ASIC module compiler. CAM is used to perform parallel search, data search using inexact match capability, and logical operation, but a new and easy design method is required to adopt CAM in ASIC design. To generate CAMs of various architectures, research on the CAM architecture is performed. As a result, reconfigurable leaf... View full abstract»

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  • A single-chip, asynchronous echo canceller for high-speed data communication

    Publication Year: 1995, Page(s):181 - 184
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (420 KB)

    A single-chip, 128-coefficient, asynchronous echo canceller has been developed. Cancellation is performed by an FIR filter whose coefficients are adapted using the power-of-two modified LMS algorithm. The pipelined circuit updates all coefficients and generates the filtered output every cycle while allowing a sampling rate greater than 205 kHz View full abstract»

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  • Extraction of source/drain resistance from layout for 0.5 μm non-salicide process technology

    Publication Year: 1995, Page(s):157 - 159
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    Scaling of non-salicide processes to the deep sub-micron regime will require that circuit simulators take into account sheet resistances. An accurate simulator to extract source and drain resistances from the circuit layout has been developed. The degradation of saturation drain current is most significant for increased parasitic source resistance, and the reduction of linear drain current is sign... View full abstract»

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  • A BiCMOS read channel two-chip combo for magneto-optical disk drives

    Publication Year: 1995, Page(s):325 - 328
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    A read channel two-chip processor for rewritable 3.5" magneto-optical disk drives is presented. The front-end includes an automatic gain control (AGC) circuit, a programmable 6-pole 2-zero equiripple filter/equalizer, a DC restore circuit, and pulse detectors. The back-end contains a frequency synthesizer and a data synchronizer with 3:1 operating range to support a constant density recording with... View full abstract»

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  • VLSI implementation of a 32-bit Kozen formulation Ladner/Fischer parallel prefix adder

    Publication Year: 1995, Page(s):57 - 59
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    As modern processors' word lengths increase and clock cycle times get shorter, it becomes more and more important to have basic arithmetic functions which can be used without becoming a bottleneck. The parallel prefix adder has depth O(log n) and area O(n). Since the parallel prefix adder has a regular structure with very limited fan-out, it is ideally suited for use in VLSI applications View full abstract»

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  • A high-performance ROM compiler for 0.50 μm and 0.36 μm CMOS technologies

    Publication Year: 1995, Page(s):370 - 373
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    A ROM compiler has been developed for use in IBM's 0.50 μm and 0.36 μm CMOS ASIC technologies. Late-personalized mask ROMs are generated for sizes from 512 bits to 256 K bits. The 0.50 μm technology has a memory cell area of 6.40 μm2 with a typical access time of 6.0 ns, while the 0.36 μm technology reduces memory cell area to 4.64 μm2 and has a 4.5 ns typic... View full abstract»

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  • FPGA based ATM traffic shaper for event-building networks

    Publication Year: 1995, Page(s):177 - 180
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    It has been proposed to use ATM multistage switching fabrics in high energy physics experiments to assemble the data associated with a collision, that are spread amongst many sources, and transmit it to one of many destinations where it will be analysed. This concentration of data, together with the burstiness caused by the simultaneous trigger of data sources for every event would inevitably prod... View full abstract»

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  • Transient waveform response of distributed loaded RC thin film structure for voltage step function using Laplace transformation

    Publication Year: 1995, Page(s):153 - 156
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    This paper presents closed form solution of uniformly distributed resistively loaded RC thin film structure for voltage step input function, using bisection technique, Laplace transformation, Heaviside theorem and contour integration algorithms. Two different methods are introduced: Maclorin method and iterative method. The voltage and current transient responses are plotted for different normaliz... View full abstract»

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  • Measuring the complexity of HDL models

    Publication Year: 1995, Page(s):113 - 116
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    This paper deals with the psychological complexity of HDL models. The results from software engineering regarding this topic are discussed. Then the main factors of complexity in an HDL model are identified. Following this, useful complexity measures are presented, and the meaning of their values is analyzed. Finally, the role of complexity measures for hardware design in the future is discussed View full abstract»

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  • Characteristics of interconnect delay in 0.5 micron CMOS

    Publication Year: 1995, Page(s):17 - 20
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (256 KB)

    Accurate analysis of the interconnect is imperative in contemporary sub-micron geometry circuits. The drive characteristics of the driving transistor play a significant role in the response of the interconnect. This paper presents a detailed analysis of a capacitively loaded distributed RLC system driven by a transistor. Using an analytic model the performance of the interconnect will be character... View full abstract»

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  • Single chip array processor for high performance design error simulation

    Publication Year: 1995, Page(s):338 - 341
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    This paper describes a single chip massively parallel special array processor which can be used as a new high performance accelerator for design error simulation. The new accelerator adopts simple logic element and communication interface with minimum transistors. Using this, high speed simulation can be performed View full abstract»

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  • Circuit techniques for standby mode/Iddq test compatible voltage comparators

    Publication Year: 1995, Page(s):216 - 217
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    This paper describes the means for IDDQ (quiescent supply current) testing of digital and mixed signal systems that contain analog circuits. A simple comparator design is presented that has been modified to be IDDQ test compatible. A by product of IDDQ test compatibility is a standby state that allows for a significant reduction in the IDDQ of the circuit, and an output data retention capability View full abstract»

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  • Designing PCI bus interfaces with programmable logic

    Publication Year: 1995, Page(s):321 - 324
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (412 KB)

    PCI-compliant high-density programmable logic devices can be used to create flexible PCI bus interfaces while avoiding the costs and risks of custom IC development. However, careful design is required to meet the performance and signaling requirements of the PCI specification. This paper focuses on the attributes needed in programmable logic devices to facilitate interface design, and suggests app... View full abstract»

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  • Optimized placement of boundary scan circuitry on semi-custom ASICs

    Publication Year: 1995, Page(s):207 - 210
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    This paper presents strategies for an optimized placement of Boundary Scan test circuitry on semi-custom ASICs. It includes rules for an optimized partitioning of the BS Logic into different logical blocks as well as rules for an area-optimized implementation of these blocks. It exemplifies that Boundary Scan test of semi-custom ASICs can be feasible regardless of complexity and fabrication volume View full abstract»

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  • Full custom CMOS design and measurement of a video D/A converter

    Publication Year: 1995, Page(s):275 - 278
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    This paper describes the design and testing of a video 8-bit D/A converter, based on 63 binary non-weighted current cells, arranged in a 8×8 matrix for the 6 MSBs and 2 binary weighted current cells for the 2 LSBs. Each current cell is provided with a balanced output. Cascode transistors are used to increase the accuracy and speed of the switching current cells. The design has been simulated... View full abstract»

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  • A complete 0.5 μm high performance array family

    Publication Year: 1995, Page(s):53 - 56
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    A 3.3 V CMOS gate array and embedded array family with 0.5 μm drawn channel length and three metal layers has been developed for high performance applications. With internal toggle frequency at 600 MHz, this array family can be designed to handle over 100 MHz, and even up to 200 MHz system speed. In addition, high speed I/O's, tight clock skew control methodology, embedded macros and high perfo... View full abstract»

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  • Three-dimensional field-programmable gate arrays

    Publication Year: 1995, Page(s):253 - 256
    Cited by:  Papers (29)  |  Patents (27)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    Motivated by improving FPGA performance, we propose a new three-dimensional (3D) FPGA architecture, along with a fabrication methodology. We analyze the expected manufacturing yield, and raise several physical-design issues in the new 3D paradigm. Our techniques also have good implications for resource utilization, physical size, and power consumption View full abstract»

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