By Topic

Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS. International Conference on

Date 2-5 Sept. 2007

Filter Results

Displaying Results 1 - 25 of 61
  • Proceedings

    Publication Year: 2007, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (5573 KB)
    Freely Available from IEEE
  • 2007 International conference on design & technology of integrated systems in nanoscale era

    Publication Year: 2007, Page(s): i
    Request permission for commercial reuse | PDF file iconPDF (33 KB)
    Freely Available from IEEE
  • [Breaker page]

    Publication Year: 2007, Page(s): ii
    Request permission for commercial reuse | PDF file iconPDF (456 KB)
    Freely Available from IEEE
  • [Copyright notice]

    Publication Year: 2007, Page(s): iii
    Request permission for commercial reuse | PDF file iconPDF (35 KB)
    Freely Available from IEEE
  • Foreword

    Publication Year: 2007, Page(s): iv
    Request permission for commercial reuse | PDF file iconPDF (28 KB) | HTML iconHTML
    Freely Available from IEEE
  • DTIS Organization

    Publication Year: 2007, Page(s):v - vii
    Request permission for commercial reuse | PDF file iconPDF (25 KB)
    Freely Available from IEEE
  • Referees

    Publication Year: 2007, Page(s): viii
    Request permission for commercial reuse | PDF file iconPDF (17 KB)
    Freely Available from IEEE
  • Table of contents

    Publication Year: 2007, Page(s):ix - xiv
    Request permission for commercial reuse | PDF file iconPDF (68 KB)
    Freely Available from IEEE
  • Meeting the evolving challenges of the semiconductor industry

    Publication Year: 2007, Page(s): I
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (263 KB)

    The semiconductor industry is approaching maturity. Growth expectations scaled back from historical norm Investments to stay competitive are outpacing industry growth. At the same time, customer pressure to keep costs down is relentless. Technology and product development costs are soaring. Very few companies can afford process development and manufacturing expense for leading edge technologies. T... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New strategies for system design

    Publication Year: 2007, Page(s): II
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB) | HTML iconHTML

    With complexities of systems-on-chip (SOCs) rising almost daily, the design community has been searching for a new methodology that can handle given complexities with increased productivity and decreased time-to-market. The obvious solution that comes to mind is increasing levels of abstraction, or in other words, increasing the size of the basic building blocks. However, it is not clear what thes... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modeling and quantification of substrate noise induced by interconnects in SOCs

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1009 KB) | HTML iconHTML

    Interconnects carrying high-frequency signals are of the most important sources of substrate noise. This paper computes the amount of the interconnect-induced substrate noise. We develop a substrate extraction tool based on the Finite Difference Method and combine the extracted output model with accurate interconnect models. Through simulation of the complete substrate-interconnect model, we inves... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integrated temperature sensor with digital output for SoC power management

    Publication Year: 2007, Page(s):7 - 12
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1178 KB) | HTML iconHTML

    In this paper a novel compact CMOS temperature sensor with built-in analogue to digital conversion and calibration is presented. It has been implemented in ST's 90 nm and 65 nm processes and is part of ST's low-power platform strategy to optimize SoC power consumption and performance. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A study on defect tolerance of tiles implementing universal gate functions

    Publication Year: 2007, Page(s):13 - 18
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (490 KB) | HTML iconHTML

    Quantum-dot cellular automata (QCA) are considered as the future alternative to state-of-the- art CMOS designs. The tile structures for the QCA circuit elements are proposed to enable effective modular design. This work introduces 3times3 tile structures for realizing the NNI (nand-nor-inverter) as well as the AOI (and-or-inverter) logic. The defect characterizations for such tiles are carried out... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Towards an energy efficient branch prediction scheme using profiling, adaptive bias measurement and delay region scheduling

    Publication Year: 2007, Page(s):19 - 24
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (438 KB) | HTML iconHTML

    Dynamic branch predictors account for between 10% and 40% of a processor's dynamic power consumption. This power cost is proportional to the number of accesses made to that dynamic predictor during a program's execution. In this paper we propose the combined use of local delay region scheduling and profiling with an original adaptive branch bias measurement. The adaptive branch bias measurement ta... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A OFDM module for a MB-OFDM receiver

    Publication Year: 2007, Page(s):25 - 29
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (458 KB) | HTML iconHTML

    The rules defined by FFC, for marketing and operation of UWB products, permitted the use of orthogonal frequency division multiplexing (OFDM) to implement UWB communications. MB-OFDM is taking place as good approach to UWB, for instance for wireless USB. The latest generations of FPGAs, including DSP capabilities, embedded processors and special features for I/O streaming, are being efficiently us... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Notice of Violation of IEEE Publication Principles
    HDL system-level design of O-QPSK receiver for 2.4-GHz band IEEE 802.15.4

    Publication Year: 2007, Page(s):30 - 34
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (860 KB) | HTML iconHTML

    Notice of Violation of IEEE Publication Principles

    "HDL System-Level Design of O-QPSK Receiver for 2.4-GHz Band IEEE 802.15.4"
    by Ahmed El Oualkadi, Denis Flandre
    in the Proceedings of the International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2007. DTIS, September 2007

    After careful and considered review of the content and authorship of this p... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Minimization of functional tests by statistical modelling of analogue circuits

    Publication Year: 2007, Page(s):35 - 40
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (419 KB) | HTML iconHTML

    In this paper, we address the problem of functional test compaction of analogue circuits by using a statistical model of the performances of the Circuit Under Test (CUT). The statistical model is obtained using data from a Monte Carlo simulation and uses a multi-normal law to estimate the joint probability density function (PDF) of the circuit performances at the design stage. The functional test ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Automatic analysis of memory faulty behavior in defective memories

    Publication Year: 2007, Page(s):41 - 46
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (310 KB) | HTML iconHTML

    As the complexity of memory faulty behavior increases, it is becoming more difficult to precisely identify the faults the memory exhibits. Knowledge of the precise set of faults is essential for designing an optimal set of memory tests with low test time and high fault coverage. This paper presents an automatic method to analyze the observed faulty behavior and to map it precisely into correspondi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integration of a concurrent signature monitoring mechanism in a System-on-a-Chip

    Publication Year: 2007, Page(s):47 - 51
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (411 KB) | HTML iconHTML

    In this work, an IP infrastructure is presented that provides concurrent signature monitoring to the designed system-on-a-chip (SoC). Such mechanisms ensure application code consistency and research focus integration inside high performance processor cores. A low-cost but very effective approach is offered, which has been successfully integrated in a prototype targeting safety critical application... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Low voltage four-quadrant current multiplier: An improved topology for n-well CMOS process

    Publication Year: 2007, Page(s):52 - 55
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (457 KB) | HTML iconHTML

    An analog CMOS current multiplier building block for low voltage applications using an n-well process is presented. The multiplier equations are derived to proof its linear characteristic, and then a low voltage design is proposed. Post layout simulation in a 0.35 mum AMS CMOS process and 1.5 V supply voltage shows a THD of 0.84% at 10 MHz and a frequency response bandwidth of 140 MHz. View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • CMOS buffer amplifier for wide bandwidth applications

    Publication Year: 2007, Page(s):56 - 59
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (314 KB) | HTML iconHTML

    This paper describes a new configuration of a CMOS buffer circuit. The new buffer is based on a Flipped Voltage Follower (FVF) with feedback in order to enhance the transconductance of the buffer as well as linearity. The proposed cell can be used as a very high bandwidth buffer to drive high capacitive loads. The employed feedback enhances the overall transconductance while minimizing the loading... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Front-end IP development: Basic know-how

    Publication Year: 2007, Page(s):60 - 63
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1350 KB) | HTML iconHTML

    IP reuse is a part of the solution to the well known design-gap problem. It aims at closing the gap between what semiconductor-technology is offering in terms of integration capacity, and what is practically possible to implement in silicon with current design methodologies and tools. This paper summarizes in bullet-point-style the most important issues related to front-end IP-development and intr... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Extending transaction level modeling for embedded software design and validation

    Publication Year: 2007, Page(s):64 - 69
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1064 KB) | HTML iconHTML

    In this paper, we propose to extend the Transaction Level Modeling (TLM) approach -initially intended as a higher level abstraction of Register Transfer Level (RTL) hardware (HW) design- to cope with embedded software (SW) design and validation. We aim at introducing new SW TLM concepts which will enable refinement of communication at the SW side. The proposed methodology allows system designers t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Digit recurrence divider: Optimization and verification

    Publication Year: 2007, Page(s):70 - 75
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1845 KB) | HTML iconHTML

    In this paper, we present the division computation by the SRT algorithm. This last is characterized by the linear convergence, i.e., at each iteration, one quotient digit is obtained as result. Thus, increasing a radix, the iterations number decreases, but the hardware complexity increases which involve the use of a multiplier to calculate the product of quotient digit by the divider. For this pur... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Assignment coverage, a complementary coverage metric in formal verification

    Publication Year: 2007, Page(s):76 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (868 KB) | HTML iconHTML

    Model checking is a formal verification method which proves whether a system satisfies a set of properties. After ensuring from correctness of properties, it is important to answer this question that which percent of the design was verified by the given set of properties? Coverage metrics in formal verification try to overcome this question. In this paper we will propose a new coverage metric in f... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.