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Performance, Computing, and Communications Conference, 1997. IPCCC 1997., IEEE International

Date 5-7 Feb. 1997

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Displaying Results 1 - 25 of 75
  • IEEE international performance, computing and communications conference

    Publication Year: 1997
    Request permission for commercial reuse | PDF file iconPDF (380 KB)
    Freely Available from IEEE
  • Author index

    Publication Year: 1997, Page(s): 579
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    Freely Available from IEEE
  • A fully non-blocking reliable multicast protocol with total ordering

    Publication Year: 1997, Page(s):378 - 384
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    We present an efficient protocol for reliable multicast in an asynchronous network subject to link and process failures. Our protocol preserves total ordering in the sense that as processes or communication links become faulty, each group of non-faulty processes that remain connected will agree on the same sequence of messages delivered. Even processes that get disconnected deliver messages in a c... View full abstract»

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  • An adaptive multiple access protocol for broadcast channels

    Publication Year: 1997, Page(s):371 - 377
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    A new adaptive multiple access protocol for time-slotted broadcast channels is presented. Slots are grouped into fixed-length time frame which can be dynamically assigned in either TDMA (time-division multiple access) or slotted-ALOHA mode. Initially, the users broadcast packets in the TDMA mode. If the number of unused slots in a frame exceeds a threshold value, the TDMA mode ceases in the next f... View full abstract»

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  • A distributed algorithm for constructing an Eulerian tour

    Publication Year: 1997, Page(s):94 - 100
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    We present an efficient distributed algorithm for constructing an Eulerian tour in a network. To construct an Eulerian circuit the algorithm requires (1+r)(|E||V|) messages and time units, where |E| is the number of the communication links, |V| is the number of the nodes in the underlying network graph, and 0⩽r<1. The value of r depends on the network topology and on the chosen traversal pa... View full abstract»

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  • Performance analysis using a non-invasive instruction trace mechanism

    Publication Year: 1997, Page(s):308 - 314
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (592 KB)

    NStrace is a bus-driven hardware trace facility developed for the PowerPC family of super-scalar RISC microprocessors. It uses a recording of activity on a target processor's bus to infer the sequence of instructions executed during that recording period. The instruction sequence is generated by simulating the processor using an architectural simulator. It represents the behavior of the processor ... View full abstract»

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  • Design of the ISO class 0 transport protocol: a stepwise refinement based approach

    Publication Year: 1997, Page(s):363 - 370
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    We present the design steps of the ISO Class 0 transport protocol. We apply, for this purpose our protocol synthesis algorithm. This algorithm is based on stepwise refinement of specifications written in an interpreted Petri net model. The starting point for the design is the specification of the ISO transport service. The main advantage of this design strategy is that the correctness of the desig... View full abstract»

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  • The performance of multithreading and scheduling on client-server systems

    Publication Year: 1997, Page(s):87 - 93
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    Two approaches to the improvement of the performance of client-server systems, multithreading and scheduling of servers, are investigated. Both of these approaches are observed to have a significant impact on system performance. The use of multithreading improves throughput characteristics of systems whereas the deployment of appropriate scheduling strategies at servers can produce a significant i... View full abstract»

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  • Memory reference metrics and instruction trace sampling

    Publication Year: 1997, Page(s):301 - 307
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    Trace-driven simulation models have been widely used to accurately estimate performance of proposed microarchitectures. Accuracy of the estimated performance greatly depends on the instruction traces as well as the model itself. Although long instruction traces are preferred, e.g. to fill a large cache, a trace could often be redundantly long; it might merely represent a small, tight loop. In this... View full abstract»

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  • Don't listen to Dr. Ruth-focus on performance

    Publication Year: 1997, Page(s):350 - 357
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1244 KB)

    Competitive system performance does not simply happen-it requires focused design by all system component contributors. However, before system performance can be designed into new products, performance characteristics of existing products need to be analyzed and understood. This paper reports about system performance analysis activities performed by the System Design and Performance Analysis team i... View full abstract»

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  • On the complexity of routing concurrent traffic in capacitated multistage networks

    Publication Year: 1997, Page(s):221 - 227
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (564 KB)

    This paper examines the complexity of a fundamental traffic routing problem that arises in the design of routing algorithms based on packing a given set of traffic requirements into a few number of passes through a given multistage interconnection network. Two classes of networks are considered: 3-stage networks, and a generalized class of extra-stage indirect binary n-cube networks. For the forme... View full abstract»

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  • Parsim: a parallel trace-driven simulation facility for fast and accurate performance analysis studies

    Publication Year: 1997, Page(s):291 - 297
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    One of the major impediments to pre-silicon performance analysis is the ever-increasing sizes of real workloads. This problem makes the use of trace-based simulation methods impractical in time-bound processor development projects. In this paper, we describe a simple method of speeding up trace-driven architectural simulation tools through the use of parallel processing. The PARSIM facility allows... View full abstract»

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  • The Motorola PowerPCTM PEEK profiler

    Publication Year: 1997, Page(s):342 - 349
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    PEEK (Performance Extraction and Exploration tool-Kit) is a product designed to provide software developers with the means to explore and improve various aspects of the performance of applications on PowerPC systems. PEEK has been engineered to support multiple operating systems that run on PowerPC processors, including the AIXTM, MacTM OS, and Windows NTTM operati... View full abstract»

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  • A dynamic self-healing routing strategy for ATM networks

    Publication Year: 1997, Page(s):215 - 220
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (560 KB)

    A hop-by-hop decentralized routing strategy for the ATM technology is considered, in which the traffic generated by different services is divided into classes, depending upon performance requirements. At each node traversed, all the outlets are considered and the least loaded one is chosen to carry the call, if it is capable to respect the quality of service requirements. The maximum number of cal... View full abstract»

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  • A frequency steered phase locked loop

    Publication Year: 1997, Page(s):76 - 81
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (476 KB)

    Voltage controlled oscillators (VCOs) implemented in digital VLSI IC (integrated circuit) technology typically have very poorly controlled centre frequencies and poor phase noise characteristics, thus severely limiting their use in phase locked loop (PLL) applications. The new technique presented incorporates an accurate local reference frequency into the PLL structure. The key parameters of the n... View full abstract»

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  • Voting without version numbers

    Publication Year: 1997, Page(s):139 - 145
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    Voting protocols are widely used to provide mutual exclusion in distributed systems and to guarantee the consistency of replicated data in the presence of network partitions. Unfortunately, the most efficient voting protocols require fairly complex metadata to assert which replicas are up-to-date and to denote the replicas that belong to that set. We present a much simpler technique that does not ... View full abstract»

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  • System-level computer architecture simulation: an experiment report

    Publication Year: 1997, Page(s):284 - 290
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (732 KB)

    It is important to capture performance trade-offs of various design options early in a design process. The system architects must get reliable performance projections for a design with very little detail. This information must be updated with greater accuracy as more details of the design are determined. There is an increasing demand for architectural tools which assist in making rapid decisions b... View full abstract»

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  • A robust real-time transport protocol for multimedia information retrieval in an ATM network

    Publication Year: 1997, Page(s):177 - 183
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    Interactive multimedia services require on-demand and real-time delivery of information to the subscriber over networks. The need for preserving the temporal properties of certain media imposes quality of service (QoS) requirements on the network. In this paper, we propose a deadline priority scheduling protocol to switch multimedia traffic from media servers (MS) to users. Users retrieve data fro... View full abstract»

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  • Fault-tolerant replication in networks with asynchronous communication link failures

    Publication Year: 1997, Page(s):131 - 136
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    We investigate the problem of locating data replicas in a network in order to maximize data availability. In particular, we analyze the complexity of computing optimal placements in networks in which communication link failures are asynchronous (i.e., only a single link fails at a time.) We show that placements maximizing availability for read operations minimize the status of the subtree induced ... View full abstract»

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  • Congestion avoidance with BUC (buffer utilization control) gateways and RFCN (reverse feedback congestion notification)

    Publication Year: 1997, Page(s):410 - 418
    Cited by:  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (956 KB)

    This paper proposes the BUC (buffer utilization control) algorithm, a congestion avoidance algorithm executed exclusively in a gateway we call the “BUC gateway”. The BUC gateway maintains separate queues per transport-level-conversation at each output-port. These “per-conversation-queues” are served in a round-robin manner. To control the data-flow of conversations, the BUC... View full abstract»

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  • Application of processor and L2 cache based performance monitors for use in workload characterization studies

    Publication Year: 1997, Page(s):337 - 341
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    This paper describes the first IBM system implementation using the Orca 12 cache. The Orca cache is a high performance, cost effective solution for using PowerPC 604e processors in server systems. The paper details the capabilities of the Orca performance monitor and results obtained on several workloads using the first IBM SMP value server View full abstract»

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  • A meshed VSAT satellite network architecture using an on-board ATM switch

    Publication Year: 1997, Page(s):208 - 214
    Cited by:  Papers (6)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    This paper proposes a meshed very small aperture terminal (VSAT) satellite communications network which uses an on-board processing (OBP) satellite with spot beams and cell switching capabilities. A novel approach is used for maximizing the bandwidth utilization of the satellite by performing statistical multiplexing on-board the satellite. MF-TDMA is used as the satellite multiple access protocol... View full abstract»

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  • Performance of standard and modified network protocols in a real-time application

    Publication Year: 1997, Page(s):26 - 32
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    Recent advances in computer and communications technologies have made possible the interconnection of large number of real-time training simulators via local area networks. The self-healing nature of real-time networked simulation has been found to allow for a modification based on discarding old packets whenever new state updates become available. The performance benefits obtained by implementing... View full abstract»

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  • A technique for demodulator reference recovery in the presence of large frequency offsets

    Publication Year: 1997, Page(s):69 - 75
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (436 KB)

    In burst mode systems synchronization is a key aspect. In these systems estimators become very attractive because of their fast convergence, which allows the reference parameter acquisition time to be very short. Estimators are, however, very sensitive to frequency offsets, leading to a degradation in their performance. The authors propose a novel feedforward technique for reference parameter reco... View full abstract»

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  • PAT: state machine based approach to performance modeling for PowerPCTM microprocessors

    Publication Year: 1997, Page(s):277 - 283
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (884 KB)

    The PAT (Performance Analysis Timer) has been developed and is in use at the Somerset Design Center for the purpose of estimating performance of various processor designs. PAT is a state machine based approach to modeling processor architectures. Each stage in a processor pipeline is represented by a stage in PAT. The flow of instructions through these stages is governed by state machines specifie... View full abstract»

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