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2007 IEEE International Test Conference

21-26 Oct. 2007

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Displaying Results 1 - 25 of 157
  • [Front cover]

    Publication Year: 2007, Page(s): c1
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  • [Copyright notice]

    Publication Year: 2007, Page(s): ii
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  • Table of contents

    Publication Year: 2007, Page(s):iii - xiv
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  • Welcome message

    Publication Year: 2007, Page(s): 1
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  • Steering Committee and Subcommittees

    Publication Year: 2007, Page(s):2 - 3
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  • ITC 2006 paper awards

    Publication Year: 2007, Page(s): 4
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  • Technical Program Committee

    Publication Year: 2007, Page(s):5 - 9
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  • ITC technical paper evaluation and selection process

    Publication Year: 2007, Page(s): 10
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  • Call for papers

    Publication Year: 2007, Page(s): 11
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  • Keynote address

    Publication Year: 2007, Page(s):12 - 15
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (562 KB)

    Provides an abstract of the keynote presentation and a brief professional biography of the presenter. The complete presentation was not made available for publication as part of the conference proceedings. View full abstract»

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  • TTTC: Test technology technical council

    Publication Year: 2007, Page(s):16 - 17
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  • 2007 Technical paper reviewers

    Publication Year: 2007, Page(s):18 - 23
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  • Author index

    Publication Year: 2007, Page(s):24 - 25
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  • On-chip timing uncertainty measurements on IBM microprocessors

    Publication Year: 2007, Page(s):1 - 7
    Cited by:  Papers (25)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (469 KB) | HTML iconHTML

    Timing uncertainty in microprocessors is comprised of several sources including PLL jitter, clock distribution skew and jitter, across chip device variations, and power supply noise. The on-chip measurement macro called SKITTER (SKew+jITTER) was designed to measure timing uncertainty from all combined sources by measuring the number of logic stages that complete in a cycle. This measure of complet... View full abstract»

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  • Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip

    Publication Year: 2007, Page(s):1 - 8
    Cited by:  Papers (16)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (287 KB) | HTML iconHTML

    The Niagara2 System-on-Chip is SUN Microsystem's latest processor in the Eco-sensitive CoolThreads line of multi-threaded servers. This DFT survey of the Niagara2 chip introduces the RAWWCas memory test, a Hybrid Flop Design and a fast efficient bitmapping architecture called DMO. It also showcases some excellent DFT results for this challenging system-on-chip design project. View full abstract»

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  • Test cost reduction for the AMD™ Athlon processor using test partitioning

    Publication Year: 2007, Page(s):1 - 10
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (195 KB) | HTML iconHTML

    The application of SOC-style test partitioning to a monolithic microprocessor design results in considerable benefits, including simpler and faster ATPG, reduced ECO impact, faster debug, and, most surprisingly, reduced test application time. These results challenge the orthodoxy that flat, top-level ATPG is the best method to produce an optimal pattern set. The granularity of the partitioning was... View full abstract»

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  • On ATPG for multiple aggressor crosstalk faults in presence of gate delays

    Publication Year: 2007, Page(s):1 - 7
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (522 KB) | HTML iconHTML

    Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to overall capacitance ratio. A typical long net also has multiple aggressors. In generating patterns to create maximal crosstalk noise on a net, it may not be possible to activate all aggressors logically or simultaneously... View full abstract»

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  • Silicon evaluation of longest path avoidance testing for small delay defects

    Publication Year: 2007, Page(s):1 - 10
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (414 KB) | HTML iconHTML

    This work presents a silicon evaluation of testing for small-delay defects using an approach called longest path avoidance testing. The motivation for LPA testing is to improve outgoing product quality by identifying delay defects that escape critical path delay testing. Results from experiments run on high volume production 180 nm ASIC are quantified in terms of test escapes and reliability escap... View full abstract»

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  • Which defects are most critical? optimizing test sets to minimize failures due to test escapes

    Publication Year: 2007, Page(s):1 - 10
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (447 KB) | HTML iconHTML

    Traditionally, test set quality has been estimated through fault coverage. However, even with 100% fault coverage, some defects may escape the testing process - making defect level a more accurate estimate of the quality of test. However, even the defect level may not truly capture the reliability experience of the customer. Specifically, different undetected defects will produce different failure... View full abstract»

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  • Advancements in at-speed array BIST: multiple improvements

    Publication Year: 2007, Page(s):1 - 10
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (245 KB) | HTML iconHTML

    This paper discusses the unique challenges in constructing an architecture and methodology for testing a 1 GHz 65 nm Embedded DRAM in an ASIC environment. The concepts of multiplication of both test commands and test clock frequency are discussed in detail. The novel technique of command multiplication is thoroughly explored. The inherent benefits of this design point is examined as it relates to ... View full abstract»

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  • A concurrent approach for testing address decoder faults in eFlash memories

    Publication Year: 2007, Page(s):1 - 10
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1168 KB) | HTML iconHTML

    The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like Flash. As any kind of memories, embedded Flash (eFlash) can be subjected to complex functional faults that are related to their particular technological process and to their integration density. In this paper, we address a major issue during eFlash testing, namely the test of Address dec... View full abstract»

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  • Diagnosis for MRAM write disturbance fault

    Publication Year: 2007, Page(s):1 - 9
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (949 KB) | HTML iconHTML

    To help improve quality and yield of magnetic random access memory (MRAM), we propose an adaptive diagnosis algorithm (ADA) that can efficiently identify the write disturbance fault (WDF) for MRAM. The proposed test algorithm is a March-based one, i.e., it has linear time complexity and can easily be implemented with built-in self-test (BIST). However, the proposed test method can evaluate the pro... View full abstract»

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  • Data jitter measurement using a delta-time-to-voltage converter method

    Publication Year: 2007, Page(s):1 - 7
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (389 KB) | HTML iconHTML

    This paper demonstrates a new low cost method for data jitter measurement. It shows that jitter in data steam can be accurately measured in real time by combining an interpolated data sequence with a delta-time-to-voltage converter. Experimental results using a 2.5-Gbps PRBS with injected sinusoidal jitter and DDJ are presented to illustrate the usefulness and accuracy of this method. View full abstract»

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  • New methods for receiver internal jitter measurement

    Publication Year: 2007, Page(s):1 - 10
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1372 KB) | HTML iconHTML

    We have developed three receiver internal deterministic jitter (DJ) and random jitter (RJ) measurement methods through external DJ stressing, RJ stressing, or sampling time shifting. High throughput jitter tolerance tests utilizing the receiver internal DJ and RJ are presented. Analytical formulas for receiver DJ and RJ estimation have been developed. Relevant simulations and laboratory experiment... View full abstract»

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  • A selt-testing BOST for high-frequency PLLs, DLLs, and SerDes

    Publication Year: 2007, Page(s):1 - 8
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (378 KB) | HTML iconHTML

    A built-off self-test (BOST) approach is described in which a self-testing FPGA on a device-under-test (DUT) interface board can test serializers or deserializers at serial rates up to 6.4 Gbps, and some SerDes at much higher rates. With a few on-chip undersampling latches, the same BOST can also test embedded PLLs, DLLs, clocks, and logic delays. For SerDes functions, the structurally tested para... View full abstract»

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