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2007 2nd International Design and Test Workshop

16-18 Dec. 2007

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Displaying Results 1 - 25 of 73
  • [Front cover]

    Publication Year: 2007, Page(s): C1
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  • [Breaker page]

    Publication Year: 2007, Page(s): i
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  • [Breaker page]

    Publication Year: 2007, Page(s): ii
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  • [Commentary]

    Publication Year: 2007, Page(s): iii
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  • Contributor listings

    Publication Year: 2007, Page(s):iv - v
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  • Table of contents

    Publication Year: 2007, Page(s):vi - x
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  • [Commentary]

    Publication Year: 2007, Page(s): xi
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  • Organized Panel Discussion

    Publication Year: 2007, Page(s): xii
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  • Panel Session: 2 - Developing Standard Automotive eSW Drivers

    Publication Year: 2007, Page(s): xiii
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  • Panel Session: 3 - Teaching VLSI in MEA

    Publication Year: 2007, Page(s): xiv
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  • Planning for Functional Verification Closure

    Publication Year: 2007, Page(s):xv - xvi
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1571 KB) | HTML iconHTML

    In his landmark 1986 article titled, No Silver Bullet: Essence and Accidents of Software Engineering [1], Dr. Fred Brooks observed that the inherent complexity of today's software systems are derived from four elements: 1. the complexity of the problem domain, 2. the difficulty of managing the development process, 3. the flexibility possible through software, and 4. the problems of characterizing ... View full abstract»

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  • Dual Mode PCGCs For Advanced Wireless Communications Networks

    Publication Year: 2007, Page(s):xvii - xxi
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5807 KB) | HTML iconHTML

    Parallel concatenated Gallager codes (PCGCs) are presented in two different modes of decoding. The turbo decoding mode is proposed for long, delay sensitive applications to reduce the decoding complexity, while the single matrix decoding may be used for short data oriented applications in advanced wireless communications networks. Techniques for the design, analysis, and convergence predictions of... View full abstract»

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  • [Breaker page]

    Publication Year: 2007, Page(s): 1
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  • Precise Identification of Memory Faults Using Electrical Simulation

    Publication Year: 2007, Page(s):3 - 8
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2379 KB) | HTML iconHTML

    Recently, a framework describing the space of all fault models has been established. Subsequently, it has been shown that many new faults of that space do exist. Gradually, The number and complexity of observed memory fault models has been gradually increasing. As a result, it has become increasingly difficult to identify the precise functional fault models that a memory suffers from. This paper s... View full abstract»

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  • An Investigation on Capacitive Coupling in RAM Address Decoders

    Publication Year: 2007, Page(s):9 - 14
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (597 KB) | HTML iconHTML

    In this paper, a complete analysis of address decoder delay faults due to capacitive coupling between address lines is presented. Detection conditions are used to explore the space of possible tests in order to detect these faults, resulting in new tests. The best test is proposed to be combined with other tests (while using the freedom of march tests) to target other faults. View full abstract»

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  • Multi-cycle Fault Injections in Error Detecting Implementations of the Advanced Encryption Standard

    Publication Year: 2007, Page(s):15 - 20
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2461 KB) | HTML iconHTML

    Fault injections can easily break a cryptosystem: hence, many dedicated error detection schemes have been proposed, relying on various forms of redundancy (e.g., temporal redundancy). In this paper, we analyze the error detection coverage of two AES implementations, based on the double-data-rate computation template, with emulated faults of several durations. View full abstract»

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  • A Novel Method of Test Generation for Asynchronous Circuits

    Publication Year: 2007, Page(s):21 - 24
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2527 KB) | HTML iconHTML

    Design of asynchronous circuits involves primitive structures which have local feedback loops like C-elements. Due to the presence of number of such primitive elements, the loops in asynchronous circuits are high. Increased number of loops in these cyclic asynchronous circuits makes the conventional synchronous CAD tools to fail as they are capable of only handling acyclic circuits. This makes the... View full abstract»

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  • [Breaker page]

    Publication Year: 2007, Page(s): 25
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  • A Reconfigurable and Programmable Filter for Software Defined Radio Based on a Transconductor-Capacitor Analog Array

    Publication Year: 2007, Page(s):27 - 32
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4644 KB) | HTML iconHTML

    This paper presents a reconfigurable and programmable analog array intended to support the implementation of the filter stage in a software defined radio (SDR) wireless transceiver. The analog array is designed using the transconductor-capacitor (Gm-C) technique and may implement a wide variety of analog filters of programmable order and transfer function. The filtering stage implemented by the an... View full abstract»

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  • Narrowband Interference Suppression for Direct Conversion Software Radios

    Publication Year: 2007, Page(s):33 - 37
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4203 KB) | HTML iconHTML

    Direct conversion from RF to baseband transforms received RF signals into its digital equivalent immediately after an antennae. Followed digital signal processing using the dynamically downloadable software according to a specific standard corresponding to the received signal type makes these systems incredibly flexible in terms of frequency bands and protocols used. However the broadband receiver... View full abstract»

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  • Ultra Low Power Narrow Band LNA

    Publication Year: 2007, Page(s):38 - 42
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3980 KB) | HTML iconHTML

    Ultra low powers LNAs are very challenging blocks. Shown in this paper is a design approach for less than 2.5 dB noise figure at 2.4 GHz with only 500 muA. On chip inductors in tsmc 0.13 mum technology was used with IV supply. The NQS effect is eliminated by using a capacitance parallel to Cg, in the inductive degeneration method. Low power architecture using transistors in sub-threshold mode. The... View full abstract»

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  • Bandwidth Extension of CMOS Transimpedance Amplifier Using On-Chip Spiral Inductor

    Publication Year: 2007, Page(s):43 - 46
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2575 KB) | HTML iconHTML

    This paper presents bandwidth extension of differential CMOS transimpedance amplifier (TIA) using on-chip inductor techniques. On-chip spiral inductor is connected in series with the output node to enhance the bandwidth. The effects of the inductor nonidealities are included in the design. Simple and accurate inductor lumped circuit model is used in analyzes. Simulation results show that the bandw... View full abstract»

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  • [Breaker page]

    Publication Year: 2007, Page(s): 47
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  • Improving Software Based Self - Testing for Cache Memories

    Publication Year: 2007, Page(s):49 - 54
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB) | HTML iconHTML

    Testing cache memories within the computer system environment is based on using processor instructions, which involve cache operations intermixed with RAM memory accesses. Applying test patterns to the cache and checking its behavior needs sophisticated instruction sequences. We simplify these sequences by means of the available on-chip performance monitors as well as built-in on-line error detect... View full abstract»

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  • Using Reconfigurable Computers for DSP Image Processing

    Publication Year: 2007, Page(s):55 - 60
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4745 KB) | HTML iconHTML

    Reconfigurable computers (RCs) are those parallel systems that are designed around multiple general-purpose processors and multiple field programmable gate array (FPGA) chips. These systems can leverage the synergism between conventional processors and FPGAs to provide low-level hardware functionality at the same level of programmability as general-purpose computers. RCs have proposed very high pr... View full abstract»

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