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System-on-Chip, 2007. DCAS 2007. 6th IEEE Dallas Circuits and Systems Workshop on

Date 15-16 Nov. 2007

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  • Towards Efficient Spectrum Sharing

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3660 KB) |  | HTML iconHTML  

    One hundred years of spectrum sharing based on fixed frequency allocations have led to fracturing and poor utilization. Present methods of frequency allocation combined with a reliance on fixed infrastructure threaten to halt this growth. An additional consequence is the deployment of fundamentally less robust systems, prone to disruption in major disasters or overload. This paper outlines a vision of a system that, by enabling the secondary use of spectrum on an opportunistic basis and by establishing collaboration between the users, would enable a realization of ubiquitous, robust and agile wireless systems that are able to support further traffic growth and changing demands in traffic. View full abstract»

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  • Top-Down Simulation Methodology of a Mixed-Signal Read Channel Using Standard VHDL

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (470 KB) |  | HTML iconHTML  

    This paper presents a mixed-signal system modeling and simulation methodology using an event-driven simulator that supports real-valued signals, such as standard VHDL. Success of this methodology has been demonstrated by a commercial 550 MHz Partial Response Maximum Likelihood (PRML) magnetic recording read channel. The read channel IC is of mixed-signal design type with 30% analog and 70% digital content. The digital portion has been synthesized from the RTL subset of VHDL (1987 standard). The analog part has been behaviorally modeled using the 1993 standard version of VHDL. Five abstraction levels of digital circuits modeling are also described. View full abstract»

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  • Modeling of an Electronic Noise and Media in a Magnetic Recording Read Channel Using VHDL

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (499 KB) |  | HTML iconHTML  

    This paper presents a modeling and simulation methodology of two challenging aspects of a partial response maximum likelihood (PRML) magnetic recording read channel: electronic noise and magnetic media. The methodology is based on an event-driven simulator that supports real-valued signals, such as standard VHDL. A few examples are presented for the noise source, PLL jitter/wander modeling, and magnetic media waveform creation. Success of this methodology has been demonstrated through a commercial 550 MHz PRML read channel IC. The read channel IC is of a mixed-signal design type with 30% analog and 70% digital content. View full abstract»

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  • PID-Controlled PLL for Fast Frequency-Hopped Systems

    Page(s): 1 - 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (93 KB) |  | HTML iconHTML  

    In this work, a novel aided-acquisition technique based on proportional-integral-derivative (PID) control of a phase-locked loop (PLL) is presented. This is achieved by inserting a control block into the PLL during acquisition where originally the output frequency/phase is controlled by a PI controller. This significantly reduces the settling time of the PLL which is important for certain applications such as WLANs where fast frequency-hopped spread-spectrum methods are used. Simulations show that the proposed structure reduces the settling time by 75%. View full abstract»

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  • Optimum Design of Cascaded Digital Filters in Wideband Wireless Transmitters using Genetic Algorithms

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (126 KB) |  | HTML iconHTML  

    In digitally intensive direct conversion transmitters, the baseband data is up-sampled to the RF rate. As the bandwidth of the baseband data increases, carefully designed cascaded digital filters are required in order to attenuate the wide replicas generated during the digital up-sampling process. Though design methodologies for single stage digital filters are very well established, near-optimum design of such multistage filters typically requires selection of several parameters by trial-and-error. This approach is time-consuming and does not assure the optimum solution (i.e. lowest area/power) under various performance constraints. In this paper, a genetic algorithm (GA) based generic automated search methodology for design of such cascaded filters is proposed. The proposed technique is demonstrated for digital WiMAX and WCDMA transmitters, for which near-optimal solutions appear to have been achieved in a relatively short time compared to the traditional manual design techniques. View full abstract»

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  • A 400MHz-2.4GHz Radiation-Tolerant Self-Biased Phase-Locked Loop

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (231 KB) |  | HTML iconHTML  

    This paper describes the design of a self-biased Phase-Locked Loop for radiation-tolerant applications. A novel single-to-differential converter circuit that eliminates the mismatches on the output of a phase-frequency-detector is proposed to minimize reference spurs. Design considerations for radiation-tolerant design are also described. Fabricated in a 0.25 ¿m CMOS Silicon-on-Sapphire process, the PLL achieves an operating frequency range from 400MHz to 2.4GHz. The RMS jitter of the PLL is 3.9ps at 2.4 GHz. View full abstract»

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  • A Speed- and Accuracy-Enhanced On-Chip Current Sensor with Local Shunt Feedback for Current-Mode Switching DC-DC Converters

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (358 KB) |  | HTML iconHTML  

    A high-speed high-accuracy on-chip current sensor for current-mode switching dc-dc converters is presented in this paper. By employing local shunt feedback, the non-dominant pole in the current sensor is pushed to high frequency. Both speed and accuracy of the current sensor can then be improved simultaneously by consuming low quiescent current. The proposed current sensor for the buck converter is designed using a standard 0.35¿m CMOS process. Results show that the proposed sensor achieves at least 95% sensing accuracy and ≪50ns settling time by consuming the quiescent current of 35¿A. The sensor allows the current-mode buck converter to operate at switching frequencies up to 2MHz with a duty cycle down to 0.2. View full abstract»

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  • Layout Parasitic Interconnections Effects on High Frequency Circuits

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (425 KB) |  | HTML iconHTML  

    The rapid growth of microelectronics constantly presents new challenges to the IC designer. The physical and dynamic characteristics of wires on a die begin to dictate the topology of an integrated circuit. Second- and third-order effects are becoming important in designs built on processes smaller than 400 nm. In this paper we try to present the influence of the parasitic layout elements by showing the difference between RC and RLC parasitic extraction and simulation and their effects on the performance of a limiting amplifier used in the optic fiber transceivers. The evaluation was done using a standard 150 nm CMOS 6 metals technology. View full abstract»

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  • "Flying-Adder" PLL Based Synchronization Mechanism for Data Packet Transport

    Page(s): 1 - 5
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (178 KB) |  | HTML iconHTML  

    A novel frequency synthesis architecture, Flying-Adder architecture, has been developed in recent years. Compared with conventional PLL based frequency synthesis techniques, this new method has many unique features. Among them, the two most distinguishing ones are its instantaneous response speed and very fine frequency resolution. These features can be especially beneficial to application of data smoothing in packet-oriented transport systems. In this paper, this Flying-Adder PLL based synchronization approach is demonstrated through two real examples. View full abstract»

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  • System-on-Chip Power Consumption Refinement and Analysis

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (206 KB) |  | HTML iconHTML  

    Accurate power consumption estimation of a System-on-Chip (SoC) using modeling techniques is difficult due to the diverse mixture of processes with radically different current consumption. It is very important that these estimations will be fine tuned to the specific SoC with accurate current measurement during the design and prototyping phase. We introduce an accurate method to measure power consumption using a single measurement point and a dynamic logging algorithm. We present a demonstration tool for continuous logging of the instantaneous power consumption with an identification of the running process within the SoC. Our approach can also be used to steer the dynamic power management (DPM) of a SoC. View full abstract»

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  • A High-Performance Multi-Match Priority Encoder for TCAM-Based Packet Classifiers

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (146 KB) |  | HTML iconHTML  

    This paper introduces a high-speed and low power multi-match priority encoder design applicable in many computer and networking systems. We propose a scalable multi-match prioritizer logic circuitry that can successively find all or the first r matched inputs in a set. The design is well suited for multi-match packet classification tasks that utilize content addressable memories as the search engine. We use a data partitioning scheme to efficiently reorganize input data for further performance improvement. A VLSI implementation of our design in 0.18¿m technology can achieve speed that outperforms the conventional multi-match packet classifier design by more than an order of magnitude. Overall power consumption is reduced by more than 40% using innovative partitioning which limits the search to a small portion of TCAM cells. View full abstract»

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  • An Efficient Implementation of Scalable Architecture for Discrete Wavelet Transform On FPGA

    Page(s): 1 - 3
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (897 KB) |  | HTML iconHTML  

    This paper presents efficient reconfigurable architecture to perform discret wavelet transform. This architecture, which is based on FPGA technology, consists of a reconfigurable processing module, reconfigurable controller, data organization unit and adresse generator, and on chip memory. The reconfigurable address generator and controller handles a flexible and efficient address generation for an efficient data memory access and bandwidth. This architecture is scalable and allows processing of a continuous data flow in real time and for any number of levels. The practical working of the architecture is explained and its hardware implementation on Xilinx Virtex-5 FPGA is reported. View full abstract»

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  • A New Fast Slew Buffering Algorithm Without Input Slew Assumptions

    Page(s): 1 - 4
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (118 KB) |  | HTML iconHTML  

    As VLSI technology moves to the nanoscale regime, an ultra-fast slew buffering technique to buffer large number of nets and minimize buffering cost is highly desirable. The existing method proposed in [1] is able to efficiently perform buffer insertion with a simplified assumption on buffer input slew, however, when handling more general cases without input slew assumptions, it becomes slow despite that significant amount of buffer area savings can be obtained. In this paper, a fast buffering technique is proposed to handle this difficult general problem. Instead of building solutions from scratch, the new approach performs efficient optimizations to buffering solutions obtained with the fixed input slew assumption. Experiments on industrial netlists demonstrate that our algorithm is very effective and highly efficient. Compared to the commonly-used van Ginneken style buffering, up to 49 × speed up is obtained and often 10% buffer area is saved. Compared to the algorithm without input slew assumption proposed in [1], up to 37 × speedup can be obtained with slight sacrifice in solution quality. View full abstract»

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  • Closed form equations for inter-modulation distortion parameters in WCDMA receiver validated through measurements

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (158 KB) |  | HTML iconHTML  

    This work establishes the closed form equations that can be used to calculate the inter-modulation distortion noise in WCDMA receivers where the distortion mechanisms involve WCDMA modulated blockers. It is shown that the distortion noise depends not only on the power of the blockers but also on the number of channels in the modulated blocker. Simple equations have been provided which can be easily used by circuit designers in each case. The equations have been validated by a direct conversion receiver chip measurements as well as MATLAB simulations. View full abstract»

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  • A CMOS Wideband LNA Using Multiple Phase Matched Frequency Staggered Resonators

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (122 KB) |  | HTML iconHTML  

    A new architecture for wideband LNAs is introduced. High gain is obtained through use of narrowband tuned stages and broadband performance is simultaneously achieved by using multiple of them, with their resonant frequencies staggered, in parallel. Multipath phase matching is shown to be effective in optimizing passband gain and NF through analysis and simulation. This topology gives advantage with respect to broadband noise performance over conventional cascaded narrowband matching network based designs and considerable power reduction at similar gain in comparison to typical distributed amplifiers. Simulations in 0.13um CMOS process show 22.3 dB peak gain, 38% fractional bandwidth about 26.5-GHz, 2.8-3.8 dB NF over entire band and mid-band output P1dB of 2.6 dBm. It consumes 31 mA from 1.5 V supply. View full abstract»

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  • A Technique to Extend Tuning Range of High Frequency Quadrature VCO

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (115 KB) |  | HTML iconHTML  

    A new approach to extend the tuning range of high frequency quadrature VCO has been proposed. The method exploits the existence of two possible modes of operation, with distinct frequencies, in LC QVCOs based on a pair of coupled cores. Mode switching is achieved by choosing between two types of reactive degeneration in coupling transistors. Used along with varactor control-based continuous tuning, in an implementation in 0.13um CMOS process, the technique extends tuning range by more than 85% over varactor-only based approach at similar oscillation frequency, phase noise, power and quadrature accuracy. This method also has limited noise degradation across the entire tuning range and requires fixed amount of power for all frequencies. Consuming a total current of 11mA from 1.2V supply the QVCO exhibits simulated phase noise of -104.7 to - 106.6dBc/Hz at 1MHz offset from center frequency. The tuning range is from 17.78 to 20.64-GHz. View full abstract»

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  • Linearization of Highly-Efficient Monolithic Class E SiGe Power Amplifiers with Envelope-Tracking (ET) and Envelope-Elimination-and-Restoration (EER) at 900MHz

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (309 KB) |  | HTML iconHTML  

    The linearization of highly efficient monolithic SiGe Class E power amplifiers (PAs) using both Envelope-Tracking (ET) and Envelope-Elimination-and-Restoration (EER) techniques has been studied at 900MHz. Without applying any linearization, the fully-integrated SiGe PAs achieve power-added efficiency (PAE) of 66% with no off-chip matching. The overall PAE of an ET-linearized PA system is 45% at an output power of 20dBm for an 881MHz EDGE (Enhanced Data Rate for GSM Evolution) modulated signal. The ET-linearized PAs pass the stringent EDGE transmit spectrum mask, but the EER-linearized PAs do not. The PAE of the ET system is expected to reach ~50% with further efficiency improvement on the envelope amplifier. View full abstract»

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  • Digital FIR Filter Optimization Using Toggle-Based Power Estimation Tools

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (354 KB) |  | HTML iconHTML  

    In this paper one method of optimizing a digital finite impulse response (FIR) filter has been illustrated. The advantages and disadvantages of several architectures and of the circuit modeling were presented using a standard toggle-based method for the circuit power estimation, gate-level simulations and synthesis. We showed that we can achieve a significant power reduction from the beginning by carefully selecting the right architecture and optimizing the VHDL code description of the module. The analysis was made based on the unity delay model and not on the physical extracted layout for a 150nm technology but the method can be used for other technologies as well. View full abstract»

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  • Analysis of Third-order Intermodulation in Receiver Down-Converter Employing Multiband Feedback

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB) |  | HTML iconHTML  

    This paper presents an analysis of the third-order intermodulation characteristics of a recently reported receiver down-converter with multiband feedback and current reuse. This design not only achieves very a high gain with a low-current requirement but also provides an inherent cancellation mechanism for enhancing the linearity of the topology. By employing the signal feedback scheme, the inherent second-order nonlinearity of the tail current sources of differential pairs that are used to provide gain at baseband can be used to cancel the third-order intermodulation distortion resulting from the same devices. Circuit simulation using 0.13-¿m RF CMOS process shows an IIP3 improvement of 4 dB in comparison to its normal cascaded counterpart. View full abstract»

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  • Enhancement of Coexistence Performance in a DRP Based Multi-Radio Environment of a Mobile Phone

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4010 KB) |  | HTML iconHTML  

    The incorporation of Bluetooth and Wireless LAN transceivers in a mobile device poses design challenges associated with their coexistence with the cellular transceiver, as they often need to operate concurrently and their close proximity is inevitable. We present recently developed techniques that transform the RF and analog circuit design complexities, typically encountered when targeting coexistence performance improvements, into the digital domain, and demonstrate how these techniques allow the concurrent operation of multiple transceivers without one adversely impacting the performance of the other. The ideas presented have been implemented in Bluetooth/WLAN transceivers offered by Texas Instruments. View full abstract»

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  • Waveform Analysis and Delay Prediction in Simultaneously Switching CMOS Gate Driven Inductively and Capacitively Coupled On-Chip Interconnects

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    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB) |  | HTML iconHTML  

    This paper focuses on waveform analysis and delay estimation of a CMOS gate driven capacitively and inductively coupled interconnect for simultaneously switching inputs. A transmission line based coupled model of interconnect is used for analysis. Delays at far-end of victim are estimated for the conditions when the inputs to two coupled interconnects are switching in-phase and out-of-phase. Alpha Power Law model of MOS-transistor is used to represent the transistors in CMOS-driver. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures 90% propagation delay; transition time delay and waveform shape with good accuracy. View full abstract»

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