System-on-Chip, 2007 International Symposium on
Date 20-21 Nov. 2007
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Displaying Results 1 - 25 of 39
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A System-level Design Method for Cognitive Radio on a Reconfigurable Multi-processor Architecture
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PDF (3877 KB)
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CMOS IC Design and Verilog-A Modelling of 10-Gb/s PLL-Based Deserializer for Inter-Chip Communication in SOC
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PDF (3936 KB)
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Managing Concurrency by Supporting Object-oriented Programming with Hybrid Data-driven Control-flow Processor
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PDF (478 KB)
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A Configuration Locking Technique to Reduce the Configuration Overhead of Run-Time Reconfigurable Devices
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PDF (2570 KB)
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Algorithm for Fast Statistical Timing Analysis
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PDF (2549 KB)
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Mixed-Signal Focal-Plane Image Processor Employing Tme-domaiin Computation Architecture
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PDF (4081 KB)
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The NoCRay Graphic Accelerator: a Case-study for MP-SoC Network-on-Chip Design Methodology
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PDF (499 KB)
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A Real-Time Learning Processor Based on K-means Algorithm with Automatic Seeds Generation
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PDF (4050 KB)
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Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip Communication
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PDF (3856 KB)
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Optimal Subset Mapping And Convergence Evaluation of Mapping Algorithms for Distributing Task Graphs on Multiprocessor SoC
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PDF (3620 KB)
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FPGA Prototype of the REALJava Co-Processor
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PDF (2585 KB)
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Control and datapath decoupling in the design of a NoC switch: area, power and performance implications
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PDF (5277 KB)
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Intelligent cameras and embedded reconfigurable computing: a case-study on motion detection
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PDF (2589 KB)
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MiGra: A Task Migration Algorithm for Reducing Temperature Gradient in Multiprocessor Systems on Chip
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PDF (637 KB)
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