Solid-State Circuits Conference, 2007. ASSCC '07. IEEE Asian
Date 12-14 Nov. 2007
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Displaying Results 1 - 25 of 117
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An anti-harmonic, programmable DLL-based frequency multiplier for dynamic frequency scaling
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PDF (1288 KB)
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An optimal design of high performance interface circuit with acoustic transducer model
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PDF (1352 KB)
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A high-speed low-complexity two-parallel radix-24 FFT/IFFT processor for UWB applications
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PDF (1400 KB)
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Spread spectrum clock generator
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PDF (386 KB)
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A low spurious 14.4mW 1.8GHz CMOS FVC-based clock generator for portable SoC processors
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PDF (1437 KB)
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A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement
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PDF (1212 KB)
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A 1V 1.7mW 25GHz transformer-feedback divide-by-3 frequency divider with quadrature outputs
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PDF (1742 KB)
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A 470-μw multi-modulus injection-locked frequency divider with division ratio of 2, 3, 4, 5 and 6 in 0.13-μm CMOS
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PDF (261 KB)
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A 66–72 GHz divide-by-3 injection-locked frequency divider in 0.13-μm CMOS technology
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PDF (1230 KB)
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A 130 nm CMOS 6-bit full nyquist 3GS/s DAC
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PDF (1376 KB)
