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Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on

Date 15-17 Oct. 2007

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Displaying Results 1 - 25 of 60
  • Power invariant secure IC design methodology using reduced complementary dynamic and differential logic

    Page(s): 1 - 6
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (378 KB) |  | HTML iconHTML  

    Security of cryptographic devices (secure ICs) like smart cards has come under threat from powerful side channel attacks like Differential Power Analysis (DPA). DPA uses power consumption information leaked from the secure IC in conjunction with statistical correlation techniques to retrieve the secret key stored in the secure IC. The most effective countermeasure to resist DPA attacks is to make the power consumption of the secure IC invariant, hence uncorrelated to the input data (secret key). In hardware implementations, this can be achieved by designing the secure IC using Dynamic and Differential Logic (DDL) style. In this paper, we present a novel methodology to design DPA-resistant power invariant secure ICs using Reduced Complementary Dynamic and Differential Logic (RCDDL). The proposed methodology involves strategies to design: 1) RCDDL gates, and 2) secure circuits using RCDDL gates. Experiments show significant improvements in security strength, average power consumption and area, when compared with a similar secure DDL and non-secure static-CMOS logic design styles. View full abstract»

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  • Neuromorphic building blocks for adaptable cortical feature maps

    Page(s): 7 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (530 KB) |  | HTML iconHTML  

    ‘Time-staggered Winner-Take-All’ is a novel CMOS analog circuit that computes ‘sum of weighted inputs” implemented as floating gate pFET ‘synapse’[ 11]. Feedback circuit of the cell exploits adaptation dynamics of floating gate FETs refining its weights in response to stimulation by patterned inputs distributed over time. This paper discusses the application of ‘ts-WTA’ cell as a core learning circuit in designing adaptive neuromorphic feature selective cells for a variety of visual cortical features such as ocular dominance, orientation selectivity etc. An array of these is-WTA cells when embedded on an RC network exhibits reaction-diffusion type clustering based on feature selective response. The cell’s adaptive behavior resembles Stent’s physiological variant of competitive Hebb learning [21] and hence has potential to act as a building block in design of adaptable feature maps in different cortices. View full abstract»

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  • An analog programmable multi-dimensional radial basis function based classifier

    Page(s): 13 - 18
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (362 KB) |  | HTML iconHTML  

    A compact analog programmable multi-dimensional radial basis function (RBF) based classifier is demonstrated. The probability distribution of each feature in the templates modeled by a Gaussian function is approximately realized by the transfer characteristics of a floating-gate bump circuit. The maximum likelihood, the mean, and the variance can be inde- pendently programmed. By cascading these floating-gate bump circuits, the transfer characteristics approximate a multivariate Gaussian function with a diagonal covariance matrix. An array of these circuits constitute a compact multi-dimensional RBF- based classifier. When followed by a winner-take-all circuit, the RBF-based classifier forms an analog vector quantizer. We use receiver operating characteristic curves and equal error rate to evaluate the performance of our analog classifiers. We show that the analog classifier performance is comparable to that of digital counterparts. The proposed approach can be at least two orders of magnitude more power efficient than the digital microprocessors at the same task. View full abstract»

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  • ReCPU: A parallel and pipelined architecture for regular expression matching

    Page(s): 19 - 24
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB) |  | HTML iconHTML  

    Text pattern matching is one of the main and most computation intensive parts of systems such as Network Intrusion Detection Systems and DNA Sequencing Matching. Software solutions to this are available but often they do not satisfy the requirements in terms of performance. This paper presents a new hardware approach for regular expression matching: ReCPU. The proposed solution is a parallel and pipelined architecture able to deal with the common regular expression semantics. This implementation based on several parallel units achieves a throughput of more than one character per clock cycle (maximum performance of state of the art solutions) requiring just O(n) memory locations (where n is the length of the regular expression). Performance has been evaluated synthesizing the VHDL description. Area and time constraints have been analyzed. Experimental results are obtained simulating the architecture. View full abstract»

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  • Use of gray decoding for implementation of symmetric functions

    Page(s): 25 - 30
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB) |  | HTML iconHTML  

    This paper discusses reduction of the number of product terms in representation of totally symmetric Boolean functions by Sum of Products (SOP) and Fixed Polarity Reed- Muller (FPRM) expansions. The suggested method reduces the number of product terms, correspondingly, the implementation cost of symmetric functions based on these expressions by exploiting Gray decoding of input variables. Although this decoding is a particular example of all possible linear transformation of Boolean variables, it is efficient in the case of symmetric functions since it provides a significant simplification of SOPs and FPRMs. Mathematical analysis as well as experimental results demonstrate the efficiency of the proposed method. View full abstract»

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  • Parametric structure-preserving model order reduction

    Page(s): 31 - 36
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB) |  | HTML iconHTML  

    Analysis and verification environments for next- generation nano-scale RFIC designs must be able to cope with increasing design complexity and to account for new effects, such as process variations and Electromagnetic (EM) couplings. Designed-in passives, substrate, interconnect and devices can no longer be treated in isolation as the interactions between them are becoming more relevant in the behavior of the complete system. At the same time variations in process parameters lead to small changes in the device characteristics that may directly affect system performance. These two effects, however, can not be treated separately as the process variations that modify the physical parameters of the devices also affect those same EM couplings. Accurately capturing the effects of process variations as well as the relevant EM coupling effects requires detailed models that become very expensive to simulate. Reduction techniques able to handle parametric descriptions of linear systems are necessary in order to obtain better simulation performance. In this work Model Order Reduction techniques able to handle parametric system descriptions are presented. Such techniques are based on Structure-Preserving formulations that are able to exploit the hierarchical system representation of designed- in blocks, substrate and interconnect, in order to obtain more efficient simulation models. View full abstract»

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  • Hierarchical statistical analysis of performance variation for continuous-time delta-sigma modulators

    Page(s): 37 - 41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (131 KB) |  | HTML iconHTML  

    Statistical analysis has become increasingly important with increasing process parameter variations in manufacturing. Monte Carlo method has been most popular for statistical analysis, but it is not efficient for complex circuits/systems due to overwhelming computational time. In this paper, we present a general hierarchical method for efficient statistical analysis of performance parameter variations for complex circuits/systems and conduct a case study on a 4th order continuous-time Delta Sigma modulator. At circuit-level, we use response surface modeling method to extract quadratic models of circuit- level performance parameters in terms of process parameter variations. Then, at system-level, we use behavioral models to extract statistical distribution of the overall system performance parameter. The method can achieve a good tradeoff between computational efficiency and accuracy. View full abstract»

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  • Regression based circuit matrix models for accurate performance estimation of analog circuits

    Page(s): 48 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (226 KB) |  | HTML iconHTML  

    Automated analog circuit synthesis techniques depend on fast and reliable estimation of circuit performance. This paper presents a highly accurate method of estimating performances by constructing models of the circuit matrix instead of the traditionally used performance models. Device matching in analog circuits is utilized to identify identical elements in the circuit matrix and reduce the number of elements to be modeled. Experiments conducted on three operational amplifier topologies demonstrate the effectiveness of the method in achieving correct performance prediction. Results show that the performances can be predicted within a mean error of 0.1% compared to a SPICE simulation. View full abstract»

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  • A software-supported methodology for designing high-performance 3D FPGA architectures

    Page(s): 54 - 59
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1628 KB) |  | HTML iconHTML  

    A software-supported systematic methodology for exploring and evaluating alternative 3D reconfigurable FPGA architectures is introduced. Two new software tools were developed: (i) a placement and routing tool for 3D FPGAs (3DPRO) and (H) a power/energy consumption estimation tool for such architectures (3DPower). Both of them are part of the new Design Framework, named 3D-MEANDER. We mainly focus our exploration on parameters that dominate the maximum operation frequency of the 3D FPGAs (i.e. vertical interconnections, number of layers, etc.). We evaluate the efficiency of the proposed methodology by making an exhaustive exploration for device delay, power consumption and utilized number of vertical connections for alternative 3D interconnection schemes. Experimental results demonstrate the effectiveness of our methodology, considering the 20 largest MCNC benchmarks. We achieve an average decrease in the delay, the wire length, and the energy consumption of 27%, 26%, and 34%, respectively, as compared to traditional 2D FPGAs, considering 3D architectures with 50% and 70% of fabricated vias. Also, we proved that actually-utilized via links are practically independent from the number of fabricated vias of a 3D FPGA architecture. View full abstract»

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  • Estimating design time for system circuits

    Page(s): 60 - 65
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB) |  | HTML iconHTML  

    System design complexity is growing rapidly. As a result, current development costs are constantly increasing. It is becoming increasingly difficult to estimate how much time it will take to design and verify these designs, which are getting denser and increasingly more complex. To compound this problem, circuit design cost estimation still does not have a quantitative approach. Although designing a system is very resource consuming, there is little work invested in measuring, understanding, and estimating the effort required. To address part of the current shortcomings, this paper introduces μPCBComplexity, a methodology to measure and estimate PCB (printed circuit board) design effort. PCBs are the central component of many systems and require large amounts of resources to properly design and verify. μPCBComplexity consists of two main parts; a procedure to account for the contributions of the different elements in the design, and a non-linear statistical regression of experimental measures in order to determine a good design effort metric. We use μPCBComplexity to evaluate a series of design effort estimators for twelve PCB designs. By using the proposed μPCBComplexity metric, designers can estimate PCB design effort. View full abstract»

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  • Transparent acceleration of data dependent instructions for general purpose processors

    Page(s): 66 - 71
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (291 KB) |  | HTML iconHTML  

    Although transistor scaling keeps following Moore’s law, and more area is available for designers, the clock frequency and ILP rate do not present the same level of growth anymore. This way, new architectural alternatives are necessary. Reconfigurable fabric appears to be one emerging possibility: besides exploiting the parallelism among instructions, it can also accelerate sequences of data dependent ones. However, coarse grain reconfiguration wide spread usage is still withhold by the need of special tools and compilers, which clearly do not sustain the reuse of legacy code without any modification. Based on all these facts, this work proposes a new Binary Translation algorithm, implemented in hardware and working in parallel to the processor, responsible for transforming sequences of instructions at run-time to be executed on a dynamic coarse-grain reconfigurable array, tightly coupled to a traditional RISC machine. Therefore, we can take advantage of using pure combinational logic to optimize even control-flow oriented code in a totally transparent process, without any modification in the source or binary codes. Using the Simplescalar Toolset together with the embedded benchmark suite MIBench, we show performance improvements and area evaluation when comparing against traditional superscalar architectures. View full abstract»

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  • VLSI models of network-on-chip interconnect

    Page(s): 72 - 77
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1316 KB) |  | HTML iconHTML  

    We use VLSI circuit models to analyze the relative delay of interconnect subsystems for networks-on-chips (NoCs). Most work in NoCs has selected a network topology based on higher-level performance models, such as packet delay. Our model parameterizes the interconnect subsystem size by N, the number of IP cores (processors, memories, etc.) to be connected. This paper analyzes busses, crossbars, and some multi-stage networks. We compare the delay required transfer a specific amount of information (bits) between two cores. Considering the data transfer parallelism in crossbars, we make 2 different comparisons: (i) transfer between 2 devices, and (ii) parallel transfers between all devices. View full abstract»

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  • Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies

    Page(s): 78 - 83
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB) |  | HTML iconHTML  

    Statistical process variations are a critical issue for circuit design strategies to ensure high yield in sub- 100nm technologies. In this work we investigate the variability of flip flop race immunity in 130nm and 90nm low power CMOS technologies. An on-chip measurement technique with resolution of ˜1ps is used to characterize hold time violations of flip flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs. Statistical die-to die variations of hold time violations are measured various register-to-register configurations and show overall 3σ die-to-die standard deviations of 12–16% Mathematical methods to separate the measured variability between systematic and random variability are discussed, and the results presented. They show that while systematic variability is the major issue in 130nm, it is significantly decreased in 90nm technology due to better process control. Another important point is that the race immunity decreases about 30% in 90nm, showing that smaller clock skews can lead to violations in 90nm. View full abstract»

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  • AC-coupling strategy for high-speed transceivers of 10Gbps and beyond

    Page(s): 84 - 87
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (461 KB) |  | HTML iconHTML  

    AC coupling in a transmission link is preferred and often required for the functioning of high speed transceivers. But at data rate of 1OGbps and beyond, both the external AC coupling and the conventional on-chip AC coupling approaches bring in heavy burden that pushes to the fundamental limits and are difficult to afford. This paper examines the AC-coupling methods for multi-Gb/s transceivers, and points out the impairments in the existing implementations. A hybrid structure offering both the signal-bump and the AC-capacitor functions under the stringent return-loss requirements of a 1OGb/s+ I/O is proposed and implemented in 65nm standard CMOS. A sizeable 5.1pF AC capacitor is measured with ultra low parasitic expense ratio of less than 120fF. View full abstract»

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  • SWORD: A SAT like prover using word level information

    Page(s): 88 - 93
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (113 KB) |  | HTML iconHTML  

    Solvers for Boolean Satisfiabilily (SAT) are state-of-the-art to solve verification problems. But when arithmetic operations are considered, the verification performance degrades with increasing data-path width. Therefore, several approaches that handle a higher level of abstraction have been studied in the past. But the resulting solvers are still not robust enough to handle problems that mix word level structures with bit level descriptions. In this paper, we present the satisfiability solver SWORD — a SAT like solver that facilitates word level information. SWORD represents the problem in terms of modules that define operations over bit vectors. Thus, word level information and structural knowledge become available in the search process. The experimental results show that on our benchmarks SWORD is more robust than Boolean SAT, K⋆BMDs or SMT. View full abstract»

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  • Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level

    Page(s): 94 - 98
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (900 KB) |  | HTML iconHTML  

    In deep-sub-micron technologies, process variability challenges the design of high yield integrated circuits. While device critical dimensions and threshold voltage shrink, leakage currents drastically increase, threatening the feasibility of reliable dynamic logic gates. Electrical level statistical characterization of this kind of gates is essential for yield analysis. This paper proposes a yield model for dynamic logic gates based on error propagation using numerical methods. We study yield of a dynamic-NOR using static keeper. The analytical formulations can be extended to a wide range of dynamic gates (for example pre-charge dynamic gates using dynamic keeper) because we use numerical approach for the calculation of derivatives required by error propagation. The proposed methodology presents errors less than 2% as compared to Monte Carlo simulation, while increasing computational efficiency up to 50×. View full abstract»

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  • Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis

    Page(s): 99 - 104
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (170 KB) |  | HTML iconHTML  

    With shrinking feature sizes in deep sub-micron technologies, interconnect delays play a dominant role in the cycle time of digital circuits. It is essential to consider the impact of physical design during high-level synthesis. No prior work exists in literature that accounts for the topology of nets resulting from binding decisions during high-level synthesis. This paper presents a novel floorplan-aware high-level synthesis technique that uses accurate net topologies and distributed wire-delay models to guide resource allocation and binding decisions during design-space exploration. The proposed approach tightly integrates a floorplanner with a high-level synthesis binding algorithm. The location of data path modules in the floorplan is used to determine the minimal length RSMT of every net, to which the delay model is applied to accurately estimate delays of multi-terminal nets. Our results show that, when compared to previous approaches, the synthesis technique proposed in this paper reduces wire delays by as much as 48.9% in 70nm technology with an average improvement of 38.6%, and an overhead of only 3.6% in chip area View full abstract»

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  • A high-driving class-AB buffer amplifier with a new pseudo source follower

    Page(s): 105 - 109
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    A high-driving class-AB buffer amplifier, which consists of a high-gain input stage and a pseudo source follower, is proposed. The pseudo source follower consists of two same types of differential pairs rather than two complementary error amplifiers. The high-driving capability is mainly provided by the folded amplifiers. An experimental prototype buffer amplifier implemented in a 0.35-μm CMOS technology demonstrates that the circuit dissipates an average static power consumption of only 660 μW at a power supply of 3.3 V, and exhibits the slew rates of 2.7 V/μs and 3.8 V/μs for the rising and falling edges, respectively, under a 300Ω/150 pF load. The second and third harmonic distortions (HD2 and HD3) are −67 dB and −65 dB, respectively, at 20 KHz under the same load. View full abstract»

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  • A new analytical approach of the impact of jitter on continuous time delta sigma converters

    Page(s): 110 - 115
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (234 KB) |  | HTML iconHTML  

    The performances of continuous time delta sigma converters are severely affected by clock jitter and no generic technique to predict the corresponding degradations is nowadays available. This paper presents a new analytical approach to quantify the power spectral density of jitter errors. This generic computational method can be applied to all kind of delta sigma converters. Furthermore, clock imperfections are described by means of phase noise spectrum, consequently all possible type of jitters can be taken into account. This paper also describes the temporal non ideal clock models that have been created to simulate the impact of jitter on delta sigma converters and validate the theoretical results. View full abstract»

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  • Transistor level automatic layout generator for non-complementary CMOS cells

    Page(s): 116 - 121
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (335 KB) |  | HTML iconHTML  

    This paper presents a tool that makes it possible to generate full layouts of CMOS cells from its transistor level netlist in SPICE format. The tool generates the cells under a linear matrix (1I)) similar layout style and is able to support unrestricted circuit structures, continuous transistor sizing and folding. It features a transistor placement algorithm for width reduction that aims the reduction of the number of diffusion gaps and the wirelength of the internal connections. The circuit nets are routed using a negotiation-based algorithm, and an Integer Linear Programming (ILP) solver is used to compaction. The experimental results show that our methodology produces layouts competitive to exact methods. The runtimes were kept low even for cells with more than 30 transistors. View full abstract»

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  • Computing and design for software and silicon manufacturing

    Page(s): 122 - 127
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (131 KB) |  | HTML iconHTML  

    An increasing demand for higher performance, for lower power density, and for greatly expanded functionalities will determine radical changes in the future computing architectures. These widely acknowledged emerging trends are however insufficient to address all the challenges introduced by advanced silicon nanometer technologies. It is well known that manufacturability for high yield, along with design productivity and predictability and system reconfigurability for reduced NRE costs and faster time-to-market, are major problems in gigascale SoC design. Therefore, only focusing the design efforts on performance, power consumption, and throughput can hinder the potentials of the new computing architectures and limit the silicon yield. In this paper, we introduce an innovative architecture-to-silicon platform that by exploiting the concept of regularity at different levels of abstraction addresses the emerging challenges for the new computing architectures, and links system and architecture definition with silicon fabrication. View full abstract»

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  • An adaptive genetic algorithm for dynamically reconfigurable modules allocation

    Page(s): 128 - 133
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (571 KB) |  | HTML iconHTML  

    This paper aims at defining an adaptive genetic algorithm tailored for the allocation of dynamically reconfigurable modules. This algorithm can be tuned at run-time with a set of parameters to best characterize different architectural scenarios (i.e., single device or multi-FPGAs characterized by several kinds of communication infrastructures) and to adapt the performance of the algorithm itself to the scenario in which it has to operate. The proposed approach has been validated with a large set of meaningful combinations of parameters (i.e. changing the mutation or the crossover probability), in order to demonstrate the possibility of performing either a fast or an accurate allocation phase. View full abstract»

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  • New tool support and architectures in adaptive reconfigurable computing

    Page(s): 134 - 139
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB) |  | HTML iconHTML  

    Novel methods and reconfigurable architectures provide an increased design space by exploiting the dynamic and partial reconfiguration of hardware. The multi-adaptivity of this heterogeneous reconfigurable architectures reaches from adaptation to performance requirements over adaptation to power consumption in relation to an available amount of energy to adaptation to not predictable requirements from the user. Especially the unpredictable demands and requirements to a computing architecture require a high and filigree adaptivity in order to find an optimized point of operation while run- time. Additional to this issue the increased availability of electronic systems comes by introduction of novel methods for failure redundancy which can be seen as an application of this multi-adaptive system. In this contribution the ideas for a novel system approach will be presented in three parts. First the hardware and methods providing the multi-adaptivity will be presented. This is the basis for higher level design tools and opens a variety of parameters for adaptivity. The mechanisms of reconfigurability will be introduced in detail from basic knowledge to advanced mechanisms and methods. In addition the abstraction levels for manipulation the reconfigurable architecture and points to the tool support for novel reconfigurable FPGA architectures from Xilinx are sketched. View full abstract»

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  • Rate-based scheduling policy for QoS flows in networks on chip

    Page(s): 140 - 145
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB) |  | HTML iconHTML  

    Several propositions of NoC architectures claim providing quality of service (QoS) guarantees, which is essential for e.g. real time and multimedia applications. The state-of-art in NoC literature provides QoS at design time, using circuit switching and/or priority-based scheduling. Both methods optimize a given network template to achieve the QoS requirements after traffic generation and network simulation. However, modern SoCs may execute applications not devised at design time, and these may easily have its QoS requirements violated by a previously fixed NoC structure. This paper proposes a method to achieve QoS requirements in NoCs at execution time. The proposed rate-based scheduling policy is employed to determine the priority of each QoS flow being transmitted through the network. The basis of this scheduling method is the difference between the rate required by a given flow and the rate currently used by this flow. This difference corresponds to the flow priority used by the scheduler. Differently from traditional priority-based scheduling, the priority is dynamically adjusted. Preliminary results show the efficiency of the rate-based scheduling to meet QoS requirements, by comparing the proposed scheduling to priority-based scheduling. View full abstract»

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