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2007 IEEE/ACM International Conference on Computer-Aided Design

4-8 Nov. 2007

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Displaying Results 1 - 25 of 153
  • Introduction

    Publication Year: 2007, Page(s):i - ii
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  • Conference committee

    Publication Year: 2007, Page(s):iii - vii
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  • Foreword

    Publication Year: 2007, Page(s): viii
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  • Awards

    Publication Year: 2007, Page(s): ix
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  • [Commentary]

    Publication Year: 2007, Page(s): x
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  • Tutorials

    Publication Year: 2007, Page(s):xi - xiii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (110 KB) | HTML iconHTML

    Provides an abstract for each of the tutorial presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • [Commentary]

    Publication Year: 2007, Page(s):xiv - xv
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  • [Commentary]

    Publication Year: 2007, Page(s): xvi
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  • Table of contents

    Publication Year: 2007, Page(s):xvii - xxix
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  • Author index

    Publication Year: 2007, Page(s):xxx - xl
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  • [Copyright notice]

    Publication Year: 2007, Page(s): xli
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  • A fast and high-capacity electromagnetic solution for high- speed IC design

    Publication Year: 2007, Page(s):1 - 6
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1322 KB) | HTML iconHTML

    This paper proposes a fast and high-capacity electromagnetic solution, time-domain layered finite element reduction recovery (LAFE-RR) method, for high-frequency modeling and simulation of large-scale on-chip circuits. This method rigorously reduces the matrix of a multilayer system to that of a single-layer one regardless of the original problem size. More important, the matrix reduction is achie... View full abstract»

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  • Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method

    Publication Year: 2007, Page(s):7 - 10
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (462 KB) | HTML iconHTML

    In this paper, we present the first BEM impedance extraction algorithm for multiple dielectrics. The effect of multiple dielectrics is significant and efficient modeling is challenging. However, previous BEM algorithms, including Fastlmp and EastPep, assume uniform dielectric, thus causing considerable errors. The new algorithm introduces a circuit formulation which makes it possible to utilizes e... View full abstract»

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  • Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach

    Publication Year: 2007, Page(s):11 - 17
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (718 KB) | HTML iconHTML

    As technologies continue to shrink in size, modeling the effect of process variations on circuit performance is assuming profound significance. Process variations affect the on-chip performance of both active and passive components. This necessitates the inclusion of the effect of these variations on distributed interconnect structures in modeling overall circuit performance. In this work, first i... View full abstract»

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  • Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip

    Publication Year: 2007, Page(s):18 - 25
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (467 KB) | HTML iconHTML

    Configuring time-division-multiplexing (TDM) virtual circuits (VCs) for network-on-chip must guarantee conflict freedom for overlapping VCs besides allocating sufficient time slots to them. These requirements are fulfilled in the slot allocution phase. In the paper, we define the concept of a logical network (LN). Based on this concept, we develop and prove theorems that constitute sufficient and ... View full abstract»

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  • Run-time adaptive on-chip communication scheme

    Publication Year: 2007, Page(s):26 - 31
    Cited by:  Papers (10)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (911 KB) | HTML iconHTML

    During run-time varying workloads and/or constraints in embedded systems require run-time adaptivity to provide a high degree of efficiency during any operation mode/scenario. Design time decisions can often only cover certain scenarios and fail in efficiency when hard-to-predict system scenarios occur. We are presenting the first approach of an adaptive on-chip communication scheme. It provides a... View full abstract»

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  • Using functional independence conditions to optimize the performance of latency-insensitive systems

    Publication Year: 2007, Page(s):32 - 39
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1700 KB) | HTML iconHTML

    In latency-insensitive design shell modules are used to encapsulate system components (pearls) in order to interface them with the given latency-insensitive protocol and dynamically control their operations. In particular, a shell stalls a pearl whenever new valid data are not available on its input channels. We study how functional independence conditions (FIC) can be applied to the perfor... View full abstract»

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  • A geometric approach for early power grid verification using current constraints

    Publication Year: 2007, Page(s):40 - 47
    Cited by:  Papers (20)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (845 KB) | HTML iconHTML

    The verification of power grids in modern integrated circuits must start, at design time, where circuit information is unknown but could be specified or inferred from design or architectural considerations. This work builds on previously proposed techniques to deal with circuit uncertainty in the framework of linear current constraints, but proposes a cost-controlled solution, by following a geome... View full abstract»

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  • Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks

    Publication Year: 2007, Page(s):48 - 53
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (827 KB) | HTML iconHTML

    In this paper, we propose a novel stochastic method for analyzing the voltage drop variations of on-chip power grid networks with log-normal leakage current variations. The new-method, called StoEKS, applies Hermite polynomial chaos (PC) to represent the random variables in both power grid networks and input leakage currents. But different from the existing Hermit PC based stochastic simulation me... View full abstract»

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  • Parallel domain decomposition for simulation of large-scale power grids

    Publication Year: 2007, Page(s):54 - 59
    Cited by:  Papers (16)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (474 KB) | HTML iconHTML

    This paper presents fully parallel domain decomposition (DO) techniques for efficient simulation of large-scale linear circuits such as power grids. DD techniques that use non-overlapping and overlapping partitioning of power grids are described in this paper. Simulation results show that with the proposed parallel DD framework, existing linear circuit simulators can be extended to handle large-sc... View full abstract»

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  • Fast exact toffoli network synthesis of reversible logic

    Publication Year: 2007, Page(s):60 - 64
    Cited by:  Papers (22)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (490 KB) | HTML iconHTML

    The research in the field of reversible logic is motivated by its application in low-power design, optical computing and quantum computing. Hence synthesis of reversible logic has become a very important research area in the last years. In this paper exact algorithms for the synthesis of generalized Toffoli networks are considered. We present an improvement of an existing synthesis approach that i... View full abstract»

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  • A novel synthesis algorithm for reversible circuits

    Publication Year: 2007, Page(s):65 - 68
    Cited by:  Papers (12)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (506 KB) | HTML iconHTML

    In this paper, a new non-search based synthesis algorithm for reversible circuits is proposed. Compared with the widely used search-based methods, our algorithm is guaranteed to produce a result and can lead to a solution with much fewer steps. To evaluate the proposed method, several circuits taken from the literature are used. The experimental results corroborate the expected findings. View full abstract»

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  • Checking equivalence of quantum circuits and states

    Publication Year: 2007, Page(s):69 - 74
    Cited by:  Papers (19)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (480 KB) | HTML iconHTML

    Among the post-CMOS technologies currently under investigation, quantum computing (QC) holds a special place. QC offers not only extremely small size and low power, but also exponential speed-ups for important simulation and optimization problems. It also poses new CAD problems that are similar to. but more challenging, than the related problems in classical (non-quantum) CAD. such as determining ... View full abstract»

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  • A self-adjusting clock tree architecture to cope with temperature variations

    Publication Year: 2007, Page(s):75 - 82
    Cited by:  Papers (6)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (745 KB) | HTML iconHTML

    Ensuring resilience against environmental variations is becoming one of the great challenges of chip design. In this paper, we propose a self adjusting clock tree architecture, SACTA, to improve chip performance and reliability in the presence of on-chip temperature variations. SACTA performs temperature dependent dynamic clock skew scheduling to prevent timing violations in a pipelined circuit. W... View full abstract»

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  • Exploiting STI stress for performance

    Publication Year: 2007, Page(s):83 - 90
    Cited by:  Papers (30)  |  Patents (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (463 KB) | HTML iconHTML

    Starting at the 65 nm node, stress engineering to improve performance of transistors has been a major industry focus. An intrinsic stress source -shallow trench isolation -has not been fully utilized up to now for circuit performance improvement. In this paper, we present a new methodology that combines detailed placement and active-layer fill insertion to exploit STI stress for performance improv... View full abstract»

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