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Asian Test Symposium, 2007. ATS '07. 16th

Date 8-11 Oct. 2007

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Displaying Results 1 - 25 of 114
  • 16th Asian Test Symposium - Cover

    Publication Year: 2007 , Page(s): c1
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  • 16th Asian Test Symposium - Title page

    Publication Year: 2007 , Page(s): i - iii
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  • 16th Asian Test Symposium - Copyright

    Publication Year: 2007 , Page(s): iv
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  • 16th Asian Test Symposium - Table of contents

    Publication Year: 2007 , Page(s): v - xii
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  • Foreword

    Publication Year: 2007 , Page(s): xiii
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  • ATS Steering Committee

    Publication Year: 2007 , Page(s): xiv
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  • Organizing Committee

    Publication Year: 2007 , Page(s): xv
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  • Program Committee

    Publication Year: 2007 , Page(s): xvi
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  • list-reviewer

    Publication Year: 2007 , Page(s): xviii
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  • Test Technology Technical Council (TTTC) Activities Board

    Publication Year: 2007 , Page(s): xix
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  • Test Technology Educational Program (TTEP) Tutorial 1

    Publication Year: 2007 , Page(s): xxii
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (40 KB)  

    Provides an abstract for each of the presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Test Technology Educational Program (TTEP) Tutorial 2

    Publication Year: 2007 , Page(s): xxiii
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (49 KB) |  | HTML iconHTML  

    Provides an abstract for each of the presentations and a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings. View full abstract»

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  • Keynote Speech 1: New Paths for Test

    Publication Year: 2007 , Page(s): 3
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (200 KB) |  | HTML iconHTML  

    Summary form only given.Test techniques for screening defective integrated circuits (ICs) after manufacture have to consider potential defects as well as the cost. In the future, test must deal with trends including advances in IC technology which continue to reduce feature sizes, the fact that mixed-signal systems on a chip are becoming a larger fraction of the semiconductor market, and very high... View full abstract»

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  • Keynote Speech 2: Consumerization of Electronics and Nanometer Technologies: Implications on Test

    Publication Year: 2007 , Page(s): 4 - 5
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (201 KB) |  | HTML iconHTML  

    Test has long been recognized as the bridge between Design and Manufacturing. However, innovation and deep integration in design and test tools has not kept pace with the consumerization of electronics and the rapidly evolving nanometer IC design and manufacturing. As a result, the full potential of Test has not been harnessed by the mainstream semiconductor community. The consumerization of elect... View full abstract»

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  • Invited Talk 1: Testing of Power Constraint Computing

    Publication Year: 2007 , Page(s): 6
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (199 KB) |  | HTML iconHTML  

    Summary form only given. Computing trend has taken a right hand turn. Instead of utmost performance at any cost, performance level have to be capped with the maximum power dissipation affordable at any given platform. With thermal dissipation mechanisms and energy cost as the primary drivers, computing at any level, from handheld devices to high-end servers, have to be power constraint. Various in... View full abstract»

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  • Invited Talk 2: EDA to the Rescue of the Silicon Roadmap

    Publication Year: 2007 , Page(s): 7 - 8
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (203 KB) |  | HTML iconHTML  

    Since the invention of the transistor nearly six decades ago, new technology nodes have been added approximately every two years. This march of progress has yielded smaller transistors that run about 40% faster with each geometry scaling fulfilling the promise and industry-defining mantra of "smaller, faster, cheaper!", and harder to Test. Now, in the realm of 65- and 45-nanometer design and manuf... View full abstract»

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  • Invited Talk 3: Foundry Full-Scale Reliability Testing Capability Setup for Advanced Technology

    Publication Year: 2007 , Page(s): 9
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (226 KB) |  | HTML iconHTML  

    Summary form only given. To facilitate the business fast-growing and meet reliability test requirements of advanced technology development and multiple types of products, it is necessary to establish a flexible, fast-responsible, and efficient full-scale reliability testing capability. The reliability testing capability should cover all segments including technology development and qualification, ... View full abstract»

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  • The Region-Exhaustive Fault Model

    Publication Year: 2007 , Page(s): 13 - 18
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (243 KB) |  | HTML iconHTML  

    Device failure mechanisms of today's deep sub-micron processes are not well-modeled by single stuck-at faults, and hence several advanced fault models have been proposed in the past. Gate-exhaustive fault models were proposed to exercise a gate completely and then observe the resultant response at an observable output. This paper extends the gate-exhaustive fault model to target bigger regions (a ... View full abstract»

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  • Mining Sequential Constraints for Pseudo-Functional Testing

    Publication Year: 2007 , Page(s): 19 - 24
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (235 KB) |  | HTML iconHTML  

    Using DFT methods such as scan can improve testability and increase fault coverage. However, scan tests may scan in illegal or unreachable states during test application, which may result in incidental detection of functional untestable delay faults during the scan test. This paper presents novel mining techniques for fast top-down functional constraint extraction. The extracted functional constra... View full abstract»

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  • Estimating the Fault Coverage of Functional Test Sequences Without Fault Simulation

    Publication Year: 2007 , Page(s): 25 - 32
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (195 KB) |  | HTML iconHTML  

    Functional test sequences were shown to detect defects that are not detected by structural tests. They also help in avoiding overtesting. However, fault simulation to compute the stuck-at fault coverage of functional test sequences can be time consuming especially in applications where a large number of test sequences need to be evaluated and compared. To obtain fast yet accurate estimates of the ... View full abstract»

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  • Fast Bridging Fault Diagnosis using Logic Information

    Publication Year: 2007 , Page(s): 33 - 38
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (368 KB) |  | HTML iconHTML  

    In this paper, we present a diagnosis methodology targeting the whole set of bridging faults leading to either static or dynamic faulty behavior. The adopted diagnosis algorithm resorts only to logic information provided by the tester without requiring a detailed description of the fault models. It is based on an Effect-Cause analysis providing a ranked list of suspects always including the root c... View full abstract»

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  • Clues for Modeling and Diagnosing Open Faults with Considering Adjacent Lines

    Publication Year: 2007 , Page(s): 39 - 44
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (327 KB) |  | HTML iconHTML  

    Under the modern manufacturing technologies, the open defect is one of the significant issues to maintain the reliability of DSM circuits. However, the modeling and techniques for test and diagnosis for open faults have not been established yet. In this paper, we give an important clue for modeling an open fault with considering the affects of adjacent lines. Firstly, we use computer simulations t... View full abstract»

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  • Fault Dictionary Based Scan Chain Failure Diagnosis

    Publication Year: 2007 , Page(s): 45 - 52
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (202 KB) |  | HTML iconHTML  

    In this paper, we present a fault dictionary based scan chain failure diagnosis technique. We first describe a technique to create small dictionaries for scan chain faults by storing differential signatures. Based on the differential signatures stored in a fault dictionary, we can quickly identify single stuck-at fault or timing fault in a faulty chain. We further develop a novel technique to diag... View full abstract»

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  • Test Education in the Global Economy

    Publication Year: 2007 , Page(s): 53
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (251 KB)  

    Summary form only given. There is an increasing demand for test and diagnosis expertise in the global semiconductor industry, in sectors ranging from foundries to test houses, to IDM companies, and from fabless design houses to EDA companies. Test education, however remains a niche, highly specialized subject area in the graduate curriculum and is seldom covered in undergraduate classes. In this p... View full abstract»

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  • Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults

    Publication Year: 2007 , Page(s): 57 - 64
    Save to Project icon | Request Permissions | Click to expandAbstract | PDF file iconPDF (490 KB) |  | HTML iconHTML  

    Test generation methodology previously developed for crosstalk targets in the presence of manufacturing defects and process variations results in low coverage. In this paper, under a realistic assumption about the nature of manufacturing defects, we show that by incorporating two new concepts, namely, non- criticality and delay-superiority, significantly higher coverage of targets and lower test g... View full abstract»

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