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Advanced Thermal Processing of Semiconductors, 2007. RTP 2007. 15th International Conference on

Date 2-5 Oct. 2007

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  • Table of contents

    Publication Year: 2007 , Page(s): nil1 - nil10
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  • 15th IEEE International Conference on Advanced Thermal Processing of Semiconductors

    Publication Year: 2007 , Page(s): nil11
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  • [Copyright notice]

    Publication Year: 2007 , Page(s): nil12
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  • Conference Chair

    Publication Year: 2007 , Page(s): nil13
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  • Regional Chairs

    Publication Year: 2007 , Page(s): nil13
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  • Conference Committee

    Publication Year: 2007 , Page(s): nil13
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  • Call for papers

    Publication Year: 2007 , Page(s): nil14
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  • [Future events]

    Publication Year: 2007 , Page(s): nil15
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  • RTP Conference Achievement Awards

    Publication Year: 2007 , Page(s): nil16 - nil17
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  • Awards

    Publication Year: 2007 , Page(s): nil18
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  • Table of contents

    Publication Year: 2007 , Page(s): nil19 - nil26
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  • Low Temperature Thin Film Transistor Technologies

    Publication Year: 2007 , Page(s): 1 - 53
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (83781 KB)  

    Various low temperature technologies compete for a foothold. It is too early to decide which ones will win. Vacuumfree technologies have a huge potential View full abstract»

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  • Low temperature Polysilicon TFT technology for electronics on plastic

    Publication Year: 2007 , Page(s): 1 - 137
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  • PDF Not Yet Available In IEEE Xplore

    Publication Year: 2007 , Page(s): 1
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    The document that should appear here is not currently available. View full abstract»

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  • Low Temperature Plasma Deposition of Silicon Thin Films for Flexible Electronics

    Publication Year: 2007 , Page(s): 1 - 64
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  • Aiming for the Best Matching Between Ultra-Shallow Doping and Milli-To Femto-Second Activation

    Publication Year: 2007 , Page(s): 1 - 10
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2791 KB) |  | HTML iconHTML  

    Semiconductors have been successfully produced by the miniaturization of planar transistors and their transformation into a 3D structure. This innovation will realize ideal performance in electric devices. In this article, plasma doping combined with several state-of-the-art rapid thermal processing is shown to be a technology for enabling the fabrication of miniaturized 2D devices and advanced 3D structures. View full abstract»

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  • Strengths, Weaknesses, Opportunities and Threats of the Post-Silicon Technologies

    Publication Year: 2007 , Page(s): 11 - 12
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (79 KB) |  | HTML iconHTML  

    The unique characteristics of novel technological platforms, using different substrates, such as SiC, GaN, plastic, and introducing thin film processing of non-conventional materials, e.g. polymers or small organic molecules, offer the promise of widespread application in several areas, ranging from light and robust displays, to low cost photovoltaics, or to flexible radio-frequency identification (RF-ID) circuitry. This talk discusses the challenges launched by the scientific community operating in the field of the post-Si technology, and specifically by STMicroelectronics, to give an impetus for advances in materials and processing development. View full abstract»

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  • Applied Materials' Product Portfolio and Roadmap

    Publication Year: 2007 , Page(s): 13 - 17
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (986 KB) |  | HTML iconHTML  

    Applied materials played a pivotal role in the commercial acceptance of rapid thermal processing (RTP) within the semiconductor industry, largely by solving the problem of precisely measuring and controlling the temperature of silicon. Today, our RTP-based products are used for processes as varied as radical oxidation, gate oxide engineering, metal silicide annealing, and ultra shallow junction annealing spanning the temperature range from 240degC to over 1200degC. The next generation RTP - millisecond annealing - is following the same trends by providing the most production worthy yet technically capable tool in the world. View full abstract»

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  • Review on Process-Induced Strain Techniques for Advanced Logic Technologies

    Publication Year: 2007 , Page(s): 19 - 29
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (746 KB) |  | HTML iconHTML  

    We have extensively studied stress enhancing techniques to increase channel mobility starting at the 130 nm technology node and continued this towards the 45 nm node. Stressed overlayers and spacer materials, strained SOI substrates, embedded SiGe and SiC layers and their proximity effects, the impact of different silicides, stress memorization and compatibility with laser and flash anneals have been investigated. The integration of abovementioned techniques into a CMOS flow resulted in an outstanding pMOS and nMOS performance improvement, no reliability issues and no impact on short channel behavior. View full abstract»

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  • Excimer Laser Annealing of Ion-Implanted Silicon: Dopant Activation, Diffusion and Defect Formation

    Publication Year: 2007 , Page(s): 31 - 35
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (285 KB) |  | HTML iconHTML  

    Minimization of dopant diffusion during electrical activation is a crucial issue in developing sub-50 nm silicon technology. Excimer laser annealing (ELA) in the melting regime is capable of meeting the requirements on shallow junctions in terms of depth, doping concentration and abruptness. However, in order to be successfully employed it has to be demonstrated that ELA can be integrated in a device processing flow. Especially, the compatibility of ELA with other high temperature processing steps such as rapid thermal annealing (RTA) needs to be addressed. In this contribution, we report on phenomena observed for B redistribution that occur during ELA in B-implanted Si and after subsequent RTA. Specific topics to be covered include (i) B build-up at the maximum melt depth during ELA, and (ii) B activation and diffusion beyond the ELA melt depth. View full abstract»

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  • Laser Activated Radical Generation in Rapid Thermal Processing

    Publication Year: 2007 , Page(s): 37 - 40
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2103 KB) |  | HTML iconHTML  

    In the present paper it will be shown that RTP combined with laser irradiation parallel to the wafer surface yields an optimum control of chemical reactions. The technique will be discussed and results regarding the surface preparation of silicon wafers as well as the deposition of atomically controlled layers for nanoelectronics will be presented. Examples are the removal of carbon containing residuals with oxygen, and the removal of the native silicon oxide with germane at temperatures of 600degC. Besides surface preparation it will also be shown that laser assisted epitaxial processes at ultra low temperatures are possible. View full abstract»

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  • Millisecond processing beyond chip technology: From electronics to photonics

    Publication Year: 2007 , Page(s): 41 - 49
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2193 KB) |  | HTML iconHTML  

    There is a clear and increasing interest in short time annealing processing far below one second, i.e. the lower limit of Rapid Thermal Processing (RTP) called spike annealing. This was driven by the need of suppressing the so-called Transient Enhanced Diffusion in advanced boron-implanted shallow pn-junctions in silicon technology. Meanwhile the interest in flash lamp annealing (FLA) in the millisecond range spread out into other fields related to silicon technology and beyond. This paper reports on recent experiments regarding shallow junction engineering in germanium, annealing of ITO layers on glass and plastic foil to form an conductive layer as well as investigations which we did during the last years in the field of wide band gap semiconductor materials (SiC, ZnO). A more common feature evolving from our work was related to the modeling of wafer stress during millisecond thermal processing with flash lamps. Finally recent achievements in the field of silicon-based light emission basing on Metal-Oxide-Semiconductor Light Emitting Devices will be reported. View full abstract»

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  • Microwave Annealing for Low Temperature Activation of As in Si

    Publication Year: 2007 , Page(s): 51 - 56
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1775 KB) |  | HTML iconHTML  

    Microwave processing of semiconductors offers distinct advantages over conventional RTP systems in some applications. The energy contained in the microwave field can be dissipated directly into the semiconductor substrate, without the convection and conduction associated with conventional processing. In this work we describe the preliminary results of microwave annealing of heavily doped silicon layers. Contrary to previously reported application of microwave annealing which basically emulate the RTP processing conditions with fast ramping of the temperature to the high temperature, we use temperatures in the range of 400-500 degC. Although the annealing mechanism in this range of temperatures requires further investigation, we demonstrated the level of activation comparable with high temperature processing. View full abstract»

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  • Sacrificial Deuterium Passivation for Improved Interface Engineering in Gate Stack Processing

    Publication Year: 2007 , Page(s): 57 - 63
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1409 KB) |  | HTML iconHTML  

    The high reactivity of the free silicon surface and its consequence: the "omnipresent" native silicon oxide hinder the interface engineering in many processing steps of IC technology on the atomic level. Methods known to eliminate the native oxide need in most cases vacuum processing. They frequently deteriorate the atomic flatness of the silicon. Hydrogen passivation by a proper DHF (diluted HF) treatment removes the native silicon oxide without roughening the surface while simultaneously maintaining a "quasi oxide free" surface in a neutral or vacuum ambient for short time. Under such circumstances the last thermal desorption peak of hydrogen is activated at around 480-500degC where the free silicon surface suddenly becomes extremely reactive. In this study we show that deuterium passivation is a promising technology. Due to the fact that deuterium adsorbs more strongly on a Si surface than hydrogen even at room temperature, deuterium passivation does not need vacuum processing and it ensures a robust process flow. View full abstract»

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  • New Tool and New Process for Ultra High Performance for Metal/High-K Gate Dielectric Stack for Sub-45 nm CMOS Manufacturing

    Publication Year: 2007 , Page(s): 65 - 69
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1733 KB) |  | HTML iconHTML  

    Off stage power dissipation and profitability are posing fundamental and practical challenges to the scaling of Si CMOS to its limit. With escalating developmental cost, off state leakage current related power dominates the CMOS heat dissipation problem making the necessity of reducing the gate leakage current density to zero, so that the designer will get relief to focus on other imposing challenges. To continue to make big gains, as we scale down from 45 nm it is important to reduce the tool cost and turn to high-k materials. In this paper we report the results of a new process and tool to deposit metal/high-k gate dielectric stack. Hafnium oxide dielectric of 0.39 nm EOT is deposited using monolayer photoassisted deposition process on a home-built system. Our process has also reliably demonstrated the success achieved with low process induced variation of the system and this is the driving factor to convincingly make this an attractive alternate choice to existing tools. The leakage current density value reported in this paper represents the lowest value reported by anyone in the open literature. This is a major breakthrough and will have major impact on the silicon IC manufacturing. View full abstract»

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