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2007 International Conference on Field Programmable Logic and Applications

27-29 Aug. 2007

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  • [Front cover]

    Publication Year: 2007, Page(s): C1
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  • 2007 International Conference on Field Programmable Logic and Applications

    Publication Year: 2007, Page(s): ii
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  • [Copyright notice]

    Publication Year: 2007, Page(s): iii
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  • In memoriam Stamatis Vassiliadis (1951 - 2007)

    Publication Year: 2007, Page(s): iv
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  • Preface

    Publication Year: 2007, Page(s):v - vi
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  • Organizing Committee

    Publication Year: 2007, Page(s): vii
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  • Program Committee

    Publication Year: 2007, Page(s):viii - xi
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  • Steering Committee

    Publication Year: 2007, Page(s): xii
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  • Additional reviewers

    Publication Year: 2007
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  • Table of contents

    Publication Year: 2007, Page(s):xvii - xxx
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  • The Intel Geneseo Project

    Publication Year: 2007, Page(s): 1
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (56 KB)

    Summary form only given. Moore's law has enabled the current trend toward multi-core computing that is dramatically increasing performance and power efficiency. I/O interconnects are on a similar growth path of increasing performance and efficiency. As computing requirements become more complex, new strategies evolve to provide the performance necessary for data-and calculation-intensive applicati... View full abstract»

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  • System-Level Design for FPGAs

    Publication Year: 2007, Page(s): 2
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (41 KB)

    Summary form only given. Today's FPGA applications are made up of many different functional elements; hardware blocks, software modules, I/O functions and on-chip interconnect fabrics are four major categories of these elements. I will explore some of the characteristics of these categories in order to provide insight into how the creation, or synthesis, of these functional elements can be automat... View full abstract»

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  • Adventures with a Reconfigurable Research Platform

    Publication Year: 2007, Page(s): 3
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    The computer industry is at a cross-roads. The problems associated with scaling uniprocessor performance has forced all major computer manufactures to turn to multi-and many-core architectures. This sea change in processor design has created many opportunities for field programmable logic. In the RAMP project, we are developing an affordable and versatile multiprocessor emulation platform being bu... View full abstract»

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  • Redefining the FPGA for the Next Generation

    Publication Year: 2007, Page(s): 4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (45 KB) | HTML iconHTML

    Summary form only given. Over the past twenty years, FPGAs evolved from simple glue-logic chips to complex systems-on-a-chip. This change can be viewed having distinct phases, each with different architecture, tools and methodology requirements. Are we now facing another phase change? Will FPGAs continue to evolve incrementally or are we about to see a radical change in field programmable logic? T... View full abstract»

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  • Design Space Exploration of the European Option Benchmark using Hyperstreams

    Publication Year: 2007, Page(s):5 - 10
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (157 KB) | HTML iconHTML

    The benchmark of pricing a European option via Monte Carlo simulation is commonly used in financial engineering for evaluating the performance of new computational techniques and to tune the parameters of the Monte Carlo simulation for improved convergence. This paper presents a comparison of different FPGA implementations of the European option benchmark against other implementations using GPUs, ... View full abstract»

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  • Accelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable Computer

    Publication Year: 2007, Page(s):11 - 16
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3096 KB) | HTML iconHTML

    Many automatic algorithms have been proposed for analyzing magnetic resonance imaging (MRI) data sets. These algorithms allow clinical researchers to generate quantitative data analyses with consistently accurate results. With the increasingly large data sets being used in brain mapping, there has been a significant rise in the need for methods to accelerate these algorithms, as their computation ... View full abstract»

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  • Soft-Hard 3D FD-TD Solver for Non Destructive Evaluation

    Publication Year: 2007, Page(s):17 - 22
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2715 KB) | HTML iconHTML

    Modeling of physical phenomena often involves the use of complex sets of equations whose computational solution has demanding requirements in terms of memory and computing power. Finite-difference time-domain (FD-TD) method is a technique widely used nowadays in a variety of areas, such as antennas design, medical studies, circuit packaging and non destructive evaluation (NDE), having the advantag... View full abstract»

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  • Array Synthesis in Systemc Hardware Compilation

    Publication Year: 2007, Page(s):23 - 28
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (186 KB) | HTML iconHTML

    This paper discusses the mapping of arrays in a high-level SystemC description to hardware. Normally, arrays are implemented as register files using general purpose logic. Modern FPGAs however contain a large number of RAM blocks which can used to implement arrays instead. Memories have a limited number of ports and mapping arrays to multiport memories involves assigning each array access to a por... View full abstract»

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  • Floating-Point Trigonometric Functions for FPGAs

    Publication Year: 2007, Page(s):29 - 34
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (229 KB) | HTML iconHTML

    Field-programmable circuits now have a capacity that allows them to accelerate floating-point computing, but are still missing core libraries for it. In particular, there is a need for an equivalent to the mathematical library (libm) available with every processor and providing implementations of standard elementary functions such as exponential, logarithm or sine. This is all the more important a... View full abstract»

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  • A Method for Fast Hardware Specialization at Run-Time

    Publication Year: 2007, Page(s):35 - 40
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB) | HTML iconHTML

    Dynamic hardware generation is a powerful technique that can substantially reduce both the required hardware resources and the time needed to perform a calculation, reflected in an improved functional density. This performance improvement is a result of additional run-time optimizations enabled by the knowledge of values at certain inputs at runtime. However, due to the large overhead conventional... View full abstract»

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  • A Many-Core Implementation Based on the Reconfigurable Mesh Model

    Publication Year: 2007, Page(s):41 - 46
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB) | HTML iconHTML

    The reconfigurable mesh is a model for massively parallel computing for which many algorithms with very low complexity have been developed. These algorithms execute cycles of bus configuration, communication, and constant-time computation on all processing elements in a lock-step. In this paper, we investigate the use of reconfigurable meshes as coprocessors to accelerate important algorithmic ker... View full abstract»

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  • An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems

    Publication Year: 2007, Page(s):47 - 53
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (340 KB) | HTML iconHTML

    Recently, there is a surge of interests in using FPGAs for computer architecture research including applications from emulating and analyzing a new platform to accelerating mi-croarchitecural simulation speed for design space exploration. This paper proposes and demonstrates a novel usage of FPGAs for measuring the efficiency of coherent traffic of an actual computer system. Our approach employs a... View full abstract»

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  • RAMP Blue: A Message-Passing Manycore System in FPGAs

    Publication Year: 2007, Page(s):54 - 61
    Cited by:  Papers (23)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (277 KB) | HTML iconHTML

    We are developing a set of reusable design blocks and several prototype systems for emulation of multi-core architectures in FPGAs. RAMP Blue is the first of these prototypes and was designed to emulate a distributed-memory message-passing architecture. The system consists of 768-1008 MicroBlaze cores in 64-84 Virtex-II Pro 70 FPGAs on 16-21 BEE2 boards, surpassing the milestone of 1000 cores in a... View full abstract»

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  • A Radio Astronomy Correlator Optimized for the Xilinx Virtex-4 SX FPGA

    Publication Year: 2007, Page(s):62 - 67
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (855 KB) | HTML iconHTML

    This paper describes a correlator that is optimized for the Xilinx Virtex-4 SX FPGA, and its application in the SKAMP radio telescope at the Molonglo Radio Observatory. The digital backend of the SKAMP telescope consists of more than 800 Virtex-4 FPGAs. Correlation is performed between each and every pairing of antenna inputs, so the SKAMP telescope, with its 384 inputs, has approximately 74,000 a... View full abstract»

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  • TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platform

    Publication Year: 2007, Page(s):68 - 73
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB) | HTML iconHTML

    Algorithm-architecture co-exploration is hindered by the lack of efficient tools. As a consequence, designers are currently able to explore only a limited set of points in the whole design space. Therefore, a tool that can allow fast exploration of algorithmic and architectural tradeoffs in an automated manner is highly desired. In this paper, we describe TANOR an automated tool targeted for desig... View full abstract»

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