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2007 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia

4-5 Oct. 2007

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Displaying Results 1 - 25 of 39
  • [Front cover]

    Publication Year: 2007, Page(s): C1
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  • [Front cover]

    Publication Year: 2007, Page(s): 1
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  • [Front cover]

    Publication Year: 2007, Page(s): 1
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  • [Breaker page]

    Publication Year: 2007, Page(s): ii
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  • [Commentary]

    Publication Year: 2007, Page(s): iii
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  • Contributor listings

    Publication Year: 2007, Page(s): iv
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  • Table of contents

    Publication Year: 2007, Page(s):v - vi
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  • [Breaker page]

    Publication Year: 2007, Page(s): 1
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  • [Commentary]

    Publication Year: 2007, Page(s): 2
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  • [Commentary]

    Publication Year: 2007, Page(s): 3
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  • [Blank page]

    Publication Year: 2007, Page(s): 4
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  • [Breaker page]

    Publication Year: 2007, Page(s):5 - 6
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  • Interposing Flash between Disk and DRAM to Save Energy for Streaming Workloads

    Publication Year: 2007, Page(s):7 - 12
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (391 KB) | HTML iconHTML

    In computer systems, the storage hierarchy, composed of a disk drive and a DRAM, is responsible for a large portion of the total energy consumed. This work studies the energy merit of interposing flash memory as a streaming buffer between the disk drive and the DRAM. Doing so, we extend the spin-off period of the disk drive and cut down on the DRAM capacity at the cost of (extra) flash. We study t... View full abstract»

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  • Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories

    Publication Year: 2007, Page(s):13 - 18
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB) | HTML iconHTML

    This paper proposes a code placement algorithm for reducing the total energy consumption of embedded processor systems including a CPU core, on-chip and off-chip memories. Our approach exploits a noncacheable memory region for an effective use of a cache memory and as a result, reduces the number of off-chip accesses. Our algorithm simultaneously finds code layouts for a cacheable region, a scratc... View full abstract»

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  • [Breaker page]

    Publication Year: 2007, Page(s):19 - 20
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  • Network Calculus Applied to Verification of Memory Access Performance in SoCs

    Publication Year: 2007, Page(s):21 - 26
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (133 KB) | HTML iconHTML

    SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of interconnect and the off-chip DRAM port by several IP blocks makes the performance of a SoC under design hard to predict. Network calculus defines the concept of flow and has been successfully used to analyse the performance of communication networks. We propose to apply network calculus ... View full abstract»

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  • Performance Analysis of Parallel Execution of H.264 Encoder on the Cell Processor

    Publication Year: 2007, Page(s):27 - 32
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (322 KB) | HTML iconHTML

    Performance improvement by parallel execution depends on two factors: the potential parallelism of the application itself, and the optimal mapping of the application to the target architecture, which is usually very target specific. As a case study, we analyze the expected performance of parallel execution of an H.264 encoding algorithm, known as X264, on the cell processor. Considering the commun... View full abstract»

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  • Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration

    Publication Year: 2007, Page(s):33 - 38
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (199 KB) | HTML iconHTML

    This paper presents a technique for high-level power estimation of microprocessors. The technique, which is based on abstract execution profiles called 'event signatures', operates at a higher level of abstraction than commonly-used instruction-level power simulators and should thus be capable of achieving good evaluation performance. We have compared our power estimation results to those from the... View full abstract»

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  • [Breaker page]

    Publication Year: 2007, Page(s):39 - 40
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  • A Quick Safari Through the MPSoC Run-Time Management Jungle

    Publication Year: 2007, Page(s):41 - 46
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB) | HTML iconHTML

    The multiprocessor SoC (MPSoC) revolution is fueled by the need to execute multiple advanced multimedia applications on a single embedded computing platform. At design-time, the applications that will run in parallel and their respective user requirements are unknown. Hence, a run-time manager is needed to match all application needs with the available platform resources and services. Creating suc... View full abstract»

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  • Run-time Task Overlapping on Multiprocessor Platforms

    Publication Year: 2007, Page(s):47 - 52
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (311 KB) | HTML iconHTML

    Today's embedded applications often consist of multiple concurrent tasks. These tasks are decomposed into sub-tasks which are in turn assigned and scheduled on multiple different processors to achieve the optimal performance/energy combination. Previous work introduced systematical approaches to make performance-energy trade-offs explorations for each individual task and used the exploration resul... View full abstract»

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  • Adaptive mapping to resource availability for dynamic wavelet-based applications

    Publication Year: 2007, Page(s):53 - 58
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (754 KB) | HTML iconHTML

    Platforms have to cope with unpredictably varying system resource requirements, because of inter-task level dynamism. To deal with this, they have to be at least partially reconfigurable. It is then important for applications to optimally exploit the memory hierarchy under varying memory availability. Moreover, in the case of intra-task dynamism, additional unpredictability is inserted and the exp... View full abstract»

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  • Impact of Task Migration on Streaming Multimedia for Embedded Multiprocessors: A Quantitative Evaluation

    Publication Year: 2007, Page(s):59 - 64
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (209 KB) | HTML iconHTML

    Dynamic task mapping solutions based on task migration has been recently explored to perform run-time reallocation of task to maximize performance and optimize energy consumption in MPSoCs. Even if task migration can provide high flexibility, its overhead must be carefully evaluated when applied to soft real-time applications. In fact, these applications impose deadlines that may be missed during ... View full abstract»

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  • [Breaker page]

    Publication Year: 2007, Page(s):65 - 66
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  • Still Image Processing on Coarse-Grained Reconfigurable Array Architectures

    Publication Year: 2007, Page(s):67 - 72
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (287 KB) | HTML iconHTML

    Due to the increasing demands on efficiency, performance and flexibility reconfigurable computational architectures are very promising candidates in embedded systems design. Recently coarse-grained reconfigurable array architectures (CGRAs), such as the ADRES CGRA and its corresponding DRESC compiler are gaining more popularity due to several technological breakthroughs in this area. We investigat... View full abstract»

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