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TRON Project Symposium, 1992. Proceedings., Ninth

Date 2-4 Dec. 1992

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  • Proceedings. The Ninth TRON Project Symposium (Cat. No.92TH0499-4)

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    Freely Available from IEEE
  • An optimizing C compiler for the GMICRO/500 microprocessor

    Page(s): 63 - 69
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    The GMICRO/500 is a superscalar microprocessor based on the TRON specification. An optimizing C compiler for the microprocessor is under development. The compiler implements both hardware-independent optimizations and GMICRO/500-specific optimizations with a performance target of 100 MIPS at 50 MHz. The hardware-independent optimizations gave a good basis for the effective improvement of hardware/software performance. On the other hand, GMICRO-specific optimizations was a challenging problem because of the complexity of the superscalar CISC architecture. The authors describe these optimization techniques with emphasis on the implementation strategy of the GMICRO/500-specific superscalar optimization View full abstract»

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  • An RTOS allowing the gradual migration

    Page(s): 107 - 114
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    A description is given of a real-time operating system (RTOS) which can allow users to achieve the gradual migration from the ITRON kernel to the μITRON kernel. It has some risks for the user to migrate between the two ITRONs because each kernel has a different system call specification. The μITRON promises speed. The ITRON, on the other hand, provides functionality to make robust programs managing complex application areas. The authors are successfully developing a novel RTOS which has two system call interfaces for the user migration between the two ITRONs with no risk. This RTOS allows users to achieve functional migration from the ITRON to the μITRON while using the ITRON interface and almost achieving the μITRON speed View full abstract»

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  • A study on the portability of CTRON FTAM-CCL and CMISE-CCL interfaces

    Page(s): 154 - 161
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    The CTRON technical committee has planned serveral CTRON portability evaluation tests. The CTRON portability experiment step 2 concentrates on layer 3, layers 4/5, FTAM, and CMISE. The authors give an overview of FTAM and CMISE tests. The portability of FTAM and CMISE interfaces is evaluated by examining problems, time taken, and source code modification required for porting them from their original CTRON basic operating systems to another CTRON basic operating system. The results confirm that the protocol parts of FTAM and CMISE have high portability View full abstract»

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  • GMICRO/500 microprocessor: pipeline structure of superscalar architecture

    Page(s): 56 - 62
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    The GMICRO/500 pipelined instruction execution mechanism is described. The 5-stage dual-pipeline superscalar architecture is examined and examples of basic instruction execution timing are analyzed, illustrating the effect of a pipe bypass mechanism and dedicated resident branch instruction caches. The benefit of microprogram-controlled instruction execution for high-speed execution of high-level language instructions is shown. Overall GMICRO/500 performance is evaluated in Dhrystones View full abstract»

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  • Advances in ITRON specifications-supporting multiprocessor and distributed systems

    Page(s): 89 - 95
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    The design policies and overviews of the extended ITRON specifications supporting distributed systems and multiprocessor systems under investigation are described. Wide applicability and high run-time performance are primary goals of these extended specifications, which are realized by inheriting the design policy of the original specification that excessive virtualization of hardware should be avoided. The authors review the design policies of the ITRON specifications, and present how the policies are incorporated in the extended specifications. The extensions expand the application areas of ITRON and make important steps towards the realization of HFDS, which is the final goal of the TRON Project View full abstract»

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  • An ATM switching software using CTRON with distributed processing support function

    Page(s): 194 - 202
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    A description is given of the basic idea for ATM switching software using CTRON. It has a three-layer, object-oriented software architecture with distributed processing support function. The authors describe how to implement the architecture View full abstract»

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  • The multi-layered design diversity architecture: application of the design diversity approach to multiple system layers

    Page(s): 116 - 121
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    The multi-layered design diversity (MLDD) architecture achieves fault tolerance to design faults of application programs, operatoring systems, and hardware components through applying the design diversity approach to these three system layers. The introduction of design diversity into multiple system layers improves system reliability. However, its enormous costs makes it impractical. The authors solve this problem through the fact that the TRON Project standardization approach to achieve compatibility among systems is same as that of the design diversity approach. In order for the MLDD architecture to be effective in improving system reliability, a probability of a coincident error, that is, two or more independently developed implementations failing on the same input, must be low. A low coincident error rate can be achieved by using sufficiently high quality development procedures for real-life applications and different testing methods for developing multiple implementations View full abstract»

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  • Human interface with computers in everyday life

    Page(s): 2 - 12
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    The computerization of equipment making up our ordinary living environment is proceeding rapidly, and the networking of these computerized objects is likely to become a major issue in the future. Embedded microchips endow equipment with advanced functions, often bringing the need for a high level of information exchange with users. For this reason, human/machine interface (HMI) with computerized objects requires at least the same level of advancement and standardization as HMI in personal computers and workstations. The author discusses the concepts and policies being incorporated in the TRON Project's standardization of HMI, based on the above premises. He describes the `TRON Human Interface Specifications for Computers in Everyday life' as a specific result of these standardization efforts View full abstract»

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  • A universal real-time kernel based on the μITRON specification

    Page(s): 96 - 106
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    The growing variety of target processors complicates the design of applications. To reduce this complexity, a universal design environment is desired. As the first step in designing the hardware independent environment, the authors propose a universal real-time kernel specification for 8 to 32-bit microprocessors. The μITRON specification can be applied to various processors but to specify the universal specification, some decisions need to be made. The authors discuss the variations in the word length, trade-offs in hiding architectures, and other related issues. They then propose the universal specification based on the μITRON specification View full abstract»

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  • A CTRON kernel benchmark program

    Page(s): 185 - 193
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    The software used in systems for information, communication, and switching processing can be more portable and easier to maintain when these systems use layered software structures (platforms). It is therefore necessary to establish techniques for comparatively evaluating the performance of different platforms designed in conformance to the interface specifications for each layer of these hierarchical systems. The authors propose a method for using a benchmark program, to quantitatively compare kernel interface performances, which are central to the performance of CTRON-specification systems View full abstract»

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  • A DB/DC platform for real-time operating systems based on CTRON specifications

    Page(s): 163 - 171
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    A database and data communication (DB/DC) platform was developed for real-time operating systems based on CTRON specifications in order to create high performance online transaction processing systems such as network operation control systems. The DB/DC platform is designed to be portable and to achieve high performance. The authors describe the software architecture of the DB/DC platform for real-time operating systems based on CTRON specifications that supports high-level programming interfaces for transaction processing applications. The following results are shown: only 2% of the source code needs to be modified when the proposed DB/DC platform is ported to another operating system based on the CTRON specifications; the number of instructions executed in a typical transaction process is reduced by 50% compared with the former in-house DB/DC platform; and CTRON specifications fully define the functions needed to construct DB/DC platforms, so it is not necessary to define other functions to increase DB/DC platforms portability View full abstract»

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  • Portability experiment for CTRON communication control (transport layer and session layer)

    Page(s): 146 - 153
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    In Step2 of the portability experiment conducted by the CTRON Technical Committee, the authors ported CTRON-specification Extended OS (transport layer and session layer communication control programs) developed by each of the participating companies to CTRON-specification Basic OS developed by other firms to run on different hardware. The aim of this experiment is to evaluate the success of CTRON Basic Communication Control specifications. The authors outline this experiment and discuss impediments to porting CTRON Basic Communication Control products. They evaluate the scale of modified lines and the number of man-hours required for the porting process. They also suggest how to solve the problems of porting programs View full abstract»

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  • Optimizing C compiler for the TRON architecture

    Page(s): 77 - 87
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    A discussion is given on the development and effects of an optimizing C compiler for the GMICRO F32 series of 32 bit microprocessors which are available for the TRON (the real time operating system nucleus) architecture. Compiler optimizations for the TRON architecture, or the CISC (complex instruction set computer) architecture with its distinct features, were achieved through a clarification of the conflict (trade-off) between the increased execution rate and the reduced object size to produce an optimizing C compiler. In particular, the application of the `1:2 rule' to the execution rate and the object size achieved the compiler optimization for this CISC architecture. That this optimizing C compiler will accomplish the objective of applying many types of application programs written in C language to the TRON architecture View full abstract»

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  • Portability experiment for CTRON general program management

    Page(s): 137 - 145
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    To examine portability in CTRON, general program management software from CTRON extended OSs was ported across various architectures. To allow portability, various modifications to the target system and to incompatible interfaces were made. The modifications requiring the most time were to the general program management software in the source system and to the load module format in the target system. There were two portings to different architectures: in the first case, porting was achieved with modification of less than 10% of the source system's code; in the second case, less than 5% modification was needed. The authors compare the two projects, and consider the results of the two porting attempts. They examine possible areas where the CTRON specifications can be enhanced to increase the portability between Extended OSs View full abstract»

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  • TRON-specification CHIP compatibility validation

    Page(s): 47 - 55
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    The CHIP validation suite, a set of programs for confirming whether a CHIP implementation conforms to the TRON specifications or not, was completed. The validation suite applies to specification level ≪L1R≫, and tests functions of the instruction set, addressing modes, flags and exceptions, etc. These programs were made with a specially developed tool that automatically generates assembler source codes. The size of the validation suite is nearly three million steps. The authors also developed a validation environment system such as a monitor program allowing the validation suite to be run on a tested chip View full abstract»

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  • The future of advanced user interfaces in product design

    Page(s): 14 - 21
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    Future industrial products will incorporate embedded microcomputers that will require advanced graphical user interfaces (GUIs). These GUIs will incorporate innovative input and display technologies, such as gestural input, multimedia, three dimensional displays, as well as new metaphors, and agents. These technology advances present challenges and opportunities for designers of human-computer communication and interaction View full abstract»

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  • TGHC: timed guarded Horn clauses

    Page(s): 122 - 135
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    A description is given of the design principles, syntax, and semantics of the distributed real-time programming language TGHC (timed guarded Horn clauses). TGHC is a descendant of concurrent logic programming languages and it is capable of explicitly expressing time constraints by introducing the timed guard to GHC. A formal semantics of a subset of TGHC is also given View full abstract»

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  • Development of a CTRON-conformant operating system on the OKITRON-SV processor system

    Page(s): 172 - 184
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    The OKITRON series of products are microcomputer systems running a CTRON-specification operating system (OS). The latest of the series to be developed is the mid-range OKITRON-SV single-board computer system, which is reported on. OKITRON-SV is equipped with a CTRON-conformant Basic OS and Extended OS, and is intended for use as a highly functional real-time platform for communication systems. It adopts the MC68030 microprocessor in a hot-standby duplex processor configuration, and features a virtual memory system, making use of the built-in MMU (memory management unit) in the MC68030. The authors outline the hardware configuration of the system, and discuss technical issues involved in their implementation of the CTRON specifications. They further describe the system features, and the environment supporting development of application software to run on the OS View full abstract»

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  • Optimizing method of C compiler for TRON architecture

    Page(s): 70 - 76
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    A description is given of the optimizing methods used in the ANSI-C compiler for the chip based on the TRON architecture. This C compiler is designed for the TLCS-90000/TX series microprocessors. For the C compiler, unique optimizing methods for the TRON architecture are used in the routines for optimization of intermediate language and code generation, in addition to the traditional global optimizing methods, such as copy propagation, loop optimization and register calling convention. Thus the compiling performance was improved. The unique features of the TRON architecture are: chained addressing mode, and the ACB and SSTR instructions. Finally, the performance of the optimizing compiler is evaluated in the terms of the execution time and object code size View full abstract»

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  • Performance evaluation of the μ BTRON bus

    Page(s): 40 - 45
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    The μBTRON bus is a simp yet fast LAN, used to connect electronic stationery goods to the BTRON workstations. The specifications of the μBTRON bus feature fast real-time performance with the ability to transfer blocks of mass data at reasonably high speed, and cost effectiveness. Yamaha has developed the LSI, called CML2, to implement the μBTRON bus specifications. In order to confirm whether the CML2 met the expected performance requirements of the μBTRON bus, a series of tests were made and the performance parameters were actually measured. In the tests, the CML2 was built on a VME board, where 68000 MPU controlled the CML2 LSI as well as carrying out some on board test programs. The result showed that CML2's performance sufficiently met the original expectation of the μBTRON bus specifications by achieving a data transfer rate of up to 386 Kbytes per second, or a frame transfer rate of 10490 frames per second maximum View full abstract»

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  • Design and implementation of the EnableWare specification-a human-machine interface for physically challenging people

    Page(s): 23 - 39
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    EnableWare is a specification and implementation of the human-machine interface (HMI) which enables physically disabled people to access computers. The BTRON HMI specification includes the EnableWare specification in standard. This assures that physically impaired people can use BTRON with no or a little software/hardware modification. The authors first analyze the difficulties of physically impaired people to use computers. Second, they propose EnableWare functions which help motor, visually, and auditory impaired users, and the architecture realizing them. Finally, on the basis of their EnableWare implementation experience on BTRONI, they propose several architectural design guidelines for the HMI system which can be operated by the physically disabled View full abstract»

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