Date 12-14 June 2007
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Displaying Results 1 - 25 of 108
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Acknowledgement
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PDF (37 KB)
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Author index
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PDF (173 KB)
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Announcement
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PDF (137 KB)
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Executive Committees
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PDF (21 KB)
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2007 Symposium on VLSI Technology
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PDF (21 KB)
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Technical Program Committees
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PDF (21 KB)
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Conference Schedule
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PDF (47 KB)
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Contents
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PDF (90 KB)
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[Copyright notice]
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PDF (24 KB)
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2007 VLSI Technology Short Course Program "Outlook for 32nm CMOS Logic and Memory Technologies"
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PDF (35 KB)
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Dependable Integration of Full-Porous Low-k Interconnect and Low-leakage/ Low-cost Transistor for 45nm LSTP Platform
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PDF (584 KB)
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A Cost-Effective LOP/LSTP Integrated CMOS Platform Utilizing Multi-Thickness SiON Gate Dielectrics with Hafnium for 45-nm Node
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PDF (637 KB)
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Manufacturability and Speed Performance Demonstration of Porous ULK (k=2.5) for a 45nm CMOS Platform
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PDF (836 KB)
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Improving Yields of High Performance 65 nm Chips with Sputtering Top Surface of Dual Stress Liner
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PDF (789 KB)
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Improvement of Performance and Data Retention Characteristics of Sub-50nm DRAM by HfSiON Gate Dielectric
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PDF (498 KB)
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Self-Alignment Techniques to enable 40nm Trench Capacitor DRAM Technologies with 3-D Array Transistor and Single-Sided Strap
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PDF (796 KB)
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High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
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PDF (542 KB)
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Integration Friendly Dual Metal Gate Technology Using Dual Thickness Metal Inserted Poly-Si Stacks (DT-MIPS)
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PDF (923 KB)


