By Topic

16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007)

Date 15-19 Sept. 2007

Filter Results

Displaying Results 1 - 25 of 79
  • 16th International Conference on Parallel Architecture and Compilation Techniques - Cover

    Publication Year: 2007, Page(s): c1
    Request permission for commercial reuse | PDF file iconPDF (1101 KB)
    Freely Available from IEEE
  • 16th International Conference on Parallel Architecture and Compilation Techniques-Title

    Publication Year: 2007, Page(s):i - iii
    Request permission for commercial reuse | PDF file iconPDF (3568 KB)
    Freely Available from IEEE
  • 16th International Conference on Parallel Architecture and Compilation Techniques-Copyright

    Publication Year: 2007, Page(s): iv
    Request permission for commercial reuse | PDF file iconPDF (59 KB)
    Freely Available from IEEE
  • 16th International Conference on Parallel Architecture and Compilation Techniques - TOC

    Publication Year: 2007
    Request permission for commercial reuse | PDF file iconPDF (53 KB)
    Freely Available from IEEE
  • Message from the General Chair

    Publication Year: 2007, Page(s): x
    Request permission for commercial reuse | PDF file iconPDF (29 KB) | HTML iconHTML
    Freely Available from IEEE
  • Message from the Program Chair

    Publication Year: 2007
    Request permission for commercial reuse | PDF file iconPDF (30 KB) | HTML iconHTML
    Freely Available from IEEE
  • Organizing Committee

    Publication Year: 2007, Page(s): xii
    Request permission for commercial reuse | PDF file iconPDF (28 KB)
    Freely Available from IEEE
  • Program Committee

    Publication Year: 2007, Page(s): xiii
    Request permission for commercial reuse | PDF file iconPDF (28 KB)
    Freely Available from IEEE
  • Keynotes

    Publication Year: 2007, Page(s):xiv - xvii
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (41 KB)

    First Page of the Article
    View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Sponsors

    Publication Year: 2007, Page(s): xviii
    Request permission for commercial reuse | PDF file iconPDF (73 KB)
    Freely Available from IEEE
  • Architectural Support for the Stream Execution Model on General-Purpose Processors

    Publication Year: 2007, Page(s):3 - 12
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    There has recently been much interest in stream processing, both in industry (e.g., Cell, NVIDIA G80, ATI R580) and academia (e.g., Stanford Merrimac, MIT RAW), with stream programs becoming increasingly popular for both media and more general-purpose computing. Although a special style of programming called stream programming is needed to target these stream architectures, huge performance benefi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Flexible Heterogeneous Multi-Core Architecture

    Publication Year: 2007, Page(s):13 - 24
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (527 KB) | HTML iconHTML

    Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a challenge as application mixes in this environment are nonuniform. Thus, multi-core processors should be flexible enough to provide high throughput for uniform parallel applications as well as high performance for more ge... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler

    Publication Year: 2007, Page(s):25 - 38
    Cited by:  Papers (60)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB) | HTML iconHTML

    We describe a new operating system scheduling algorithm that improves performance isolation on chip multiprocessors (CMP). Poor performance isolation occurs when an application's performance is determined by the behaviour of its co-runners, i.e., other applications simultaneously running with it. This performance dependency is caused by unfair, co- runner-dependent cache allocation on CMPs. Poor p... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Software-Pipelining on Multi-Core Architectures

    Publication Year: 2007, Page(s):39 - 48
    Cited by:  Papers (3)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (522 KB) | HTML iconHTML

    It is becoming increasingly evident that multi-core chip architecture are emerging as a solution to efficiently amortizing the ever-growing number of transistors on a chip. However the success of such multi-core chips depends on the advances in system software technology, such as compiler and run-time system, in order for the application programs to exploit thread level parallelism out of original... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Speculative Decoupled Software Pipelining

    Publication Year: 2007, Page(s):49 - 59
    Cited by:  Papers (25)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (421 KB) | HTML iconHTML

    In recent years, microprocessor manufacturers have shifted their focus from single-core to multi-core processors. To avoid burdening programmers with the responsibility of parallelizing their applications, some researchers have advocated automatic thread extraction. A recently proposed technique, Decoupled software pipelining (DSWP), has demonstrated promise by partitioning loops into long-running... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Rotating Register Allocation for Enhanced Pipeline Scheduling

    Publication Year: 2007, Page(s):60 - 72
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB) | HTML iconHTML

    A rotating register file is a compiler-managed hardware renaming mechanism for overcoming the cross-iteration register overwrite problem in software pipelining [3J. It has primarily been used for software pipelining of straight-line and if-converted loops in the context of modulo scheduling. This paper proposes using rotating registers for software pipelining of loops with arbitrary control flows,... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Unified Architectural Support for Soft-Error Protection or Software Bug Detection

    Publication Year: 2007, Page(s):73 - 82
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (439 KB) | HTML iconHTML

    In this paper we propose a unified architectural support that can be used flexibly for either soft-error protection or software bug detection. Our approach is based on dynamically detecting and enforcing instruction- level invariants. A hardware table is designed to keep track of run-time invariant information. During program execution, instructions access this table and compare their produced res... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Verification-Aware Microprocessor Design

    Publication Year: 2007, Page(s):83 - 93
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (415 KB) | HTML iconHTML

    The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. However, architects do not quantify the impact of these design decisions on the effort required to verify them, potentially increasing the time to market. We propose designing processors with formal verifiability as a first-c... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems

    Publication Year: 2007, Page(s):94 - 103
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (241 KB) | HTML iconHTML

    Protection and security are becoming essential requirements in commercial servers. In this paper, we present a fast and efficient method for providing secure memory and cache-to-cache communications in shared memory multiprocessor systems that are becoming enormously popular in designing servers for various applications. Since our scheme is independent of underlying interconnects and cache coheren... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Error Detection Using Dynamic Dataflow Verification

    Publication Year: 2007, Page(s):104 - 118
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (547 KB) | HTML iconHTML

    A significant fraction of the circuitry in a modern processor is dedicated to converting the linear instruction stream into a representation that allows the execution of instructions in data dependence order, rather than program order, to extract instruction level parallelism. All errors caused by hardware faults in this circuitry - which includes the fetch and decode stages, renaming and scheduli... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Extending Object-Oriented Optimizations for Concurrent Programs

    Publication Year: 2007, Page(s):119 - 129
    Cited by:  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (515 KB) | HTML iconHTML

    Object-oriented programming encourages extensive use of fields in objects. Most object-oriented programs are also concurrent, due to a finalizer or user interface thread. The combination of concurrency and frequent use of fields presents an optimization challenge: it is difficult for an optimizer to establish invariants between fields at different points in the program and recognize redundancy int... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Language and Virtual Machine Support for Efficient Fine-Grained Futures in Java

    Publication Year: 2007, Page(s):130 - 139
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (333 KB) | HTML iconHTML

    In this work, we investigate the implementation of futures in Java J2SE v 5.0. Java 5.0 provides an interface-based implementation of futures that enables users to encapsulate potentially asynchronous computation and to define their own execution engines for futures. Although this methodology decouples thread scheduling from application logic, for applications with fine-grained parallelism, this m... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Call-chain Software Instruction Prefetching in J2EE Server Applications

    Publication Year: 2007, Page(s):140 - 149
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (543 KB) | HTML iconHTML

    We present a detailed characterization of instruction cache performance for IBM's J2EE-enabled Web server, WebSphere Application Server (WAS). When running two J2EE benchmarks on WebSphere, we find that instruction cache misses cause a 12% performance penalty on current-generation Power5-based multiprocessor systems. To mitigate this performance loss, we describe a new call-chain based algorithm f... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Detecting Change in Program Behavior for Adaptive Optimization

    Publication Year: 2007, Page(s):150 - 162
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (434 KB) | HTML iconHTML

    Feedback information has proven useful in guiding optimizations in compilers and post-link optimizers. Program performance behavior can change over time and may invalidate the feedback information. Low overhead monitoring can be used to detect such changes, using performance metrics such as CPI. On a loaded SMT system, where other threads are simultaneously activated on the same CPU, the CPI shows... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reducing Energy Consumption of On-Chip Networks Through a Hybrid Compiler-Runtime Approach

    Publication Year: 2007, Page(s):163 - 174
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (847 KB) | HTML iconHTML

    This paper investigates a compiler-runtime approach for reducing power consumption in the context of the network-on-chip (NoC) based chip multiprocessor (CMP) architectures. Our proposed approach is based on the observation that the same communication patterns across the nodes of a mesh based CMP repeat themselves in successive iterations of a loop nest. The approach collects the link usage statis... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.