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[1992] Proceedings of the International Conference on Application Specific Array Processors

4-7 Aug. 1992

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  • Proceedings of the International Conference on Application Specific Array Processors (Cat. No.92TH0453-1)

    Publication Year: 1992
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    Freely Available from IEEE
  • Interval-related problems on reconfigurable meshes

    Publication Year: 1992, Page(s):445 - 455
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (488 KB)

    Interval graphs provide a natural model for a vast number of scheduling and VLSI problems. A variety of interval graph problems have been solved on the PRAM family. Recently, a powerful architecture called the reconfigurable mesh has been proposed: in essence, a reconfigurable mesh consists of a mesh-connected architecture augmented by a dynamically reconfigurable bus system. It has been argued th... View full abstract»

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  • A parallel sorting algorithm on an eight-neighbor processor array

    Publication Year: 1992, Page(s):456 - 468
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (452 KB)

    The authors deal with a new parallel sorting algorithm on an eight-neighbor processor array with wraparounds in the rows. The algorithm is very simple because it is composed of the iteration of only a primitive operation, comparing and exchanging four elements simultaneously. Each processor (processing element), arranged in a two-dimensional array can communicate with 8 neighbouring processors (if... View full abstract»

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  • Fault tolerant matrix triangularization and solution of linear systems of equations

    Publication Year: 1992, Page(s):469 - 480
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The authors present a fault tolerant algorithm for the solution of linear systems of equations using matrix triangularization procedures suitable for implementation on array architectures. Gaussian elimination with partial or pairwise pivoting and QR decomposition are made fault tolerant against two transient errors occurring during the triangularization procedure. The extended Euclidean algorithm... View full abstract»

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  • Systolic architectures for finite-state vector quantization

    Publication Year: 1992, Page(s):481 - 495
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (448 KB)

    The authors present a new systolic architecture for implementing finite state vector quantization in real-time for both speech and image data. This architecture is modular and has a very simple control flow. Only one processor is needed for speech compression. A linear array of processors is used for image compression; the number of processors needed is independent of the size of the image. Image ... View full abstract»

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  • Matrix computations in arrays of DSPs

    Publication Year: 1992, Page(s):496 - 510
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    The authors present the use of the multimesh graph representation to map matrix algorithms onto arrays of digital signal processors (DSPs), using the TMS 320C30 as example. This processor, as most DSPs, is characterized by a two-level memory subsystem and a built-in DMA controller. The mapping process focuses on large matrices which do not fit in the first level of memory. Good utilization of the ... View full abstract»

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  • An architecture for tree search based vector quantization for single chip implementation

    Publication Year: 1992, Page(s):385 - 399
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (528 KB)

    Vector quantization (VQ) has become feasible for use in real-time applications by employing VLSI technology. The authors propose a new search algorithm and an architecture for implementing it, which can be used in real-time image processing. This search algorithm takes O (k) time units on a sequential machine, where k is the dimension of the codevectors, assuming unit ti... View full abstract»

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  • MAMACG: a tool for automatic mapping of matrix algorithms onto mesh array computational graphs

    Publication Year: 1992, Page(s):511 - 525
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    The design of MAMACG, a software tool for automatically mapping an important class of matrix algorithms into mesh array computational graphs, is described. MAMACG is a concrete realization of the multimesh graph (MMG) method, implemented in Elk, a dialect of LISP with built-in X-graphics capabilities View full abstract»

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  • A systolic array chip for robot inverse dynamics computation

    Publication Year: 1992, Page(s):400 - 414
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (600 KB)

    To ensure smooth and accurate movement of a robot arm, the robot inverse dynamics problem must be solved at each servo sampling. The computation of this problem, however, is a mathematically intense task which degrades the sampling period of presentday robot control systems. In addition to the repetitive requirement for its evaluation, the linearly recursive and computer-bound properties of the ro... View full abstract»

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  • High level software synthesis for signal processing systems

    Publication Year: 1992, Page(s):679 - 693
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (712 KB)

    For the design of complex digital signal processing systems, block diagram oriented simulation has become a widely accepted standard. Current research is concerned with the coupling of heterogenous simulation engines and the transition from simulation to the implementation of digital signal processing systems. Due to the difficulty in mastering complex design spaces high level hardware and softwar... View full abstract»

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  • Application and packaging of the AT&T DSP3 parallel signal processor

    Publication Year: 1992, Page(s):316 - 326
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (376 KB)

    Achieving the potential performance of highly parallel MIMD processor architectures is critically dependent on both the speed and routing capabilities of the network fabric. The routing network of the AT&T DSP3 processor is described together with an indication of how the 40 megabyte/s links can be configured to meet diverse application requirements. Scaling to very large configurations is aid... View full abstract»

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  • Determining longest common subsequences of two sequences on a linear array of processors

    Publication Year: 1992, Page(s):526 - 537
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    This paper presents special-purpose linear array processor architecture for determining longest common subsequences (LCS) of two sequences. The algorithm uses systolic and pipelined architectures suitable for VLSI implementation. The algorithms are also suitable for implementation on parallel machines. The author first develops a `greedy' algorithm to determine some of the LCS and then proposes a ... View full abstract»

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  • Transformation techniques for serial array design

    Publication Year: 1992, Page(s):574 - 588
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    This paper describes a design framework for developing application-specific serial array circuits. Starting from a description of the state-transition logic or a fully-parallel architecture, correctness-preserving transformations are employed to derive a wide range of implementations with different space-time trade-offs. The approach has been used in synthesising designs based on field-programmabl... View full abstract»

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  • A reconfigurable processor array with routing LSIs and general purpose DSPs

    Publication Year: 1992, Page(s):102 - 116
    Cited by:  Papers (4)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (648 KB)

    A building block for a scalable signal processor array is developed with a general-purpose DSP and a message routing LSI. Each DSP can be connected by multiple routing LSIs forming a point-to-point message-passing network with data packet communication. Low network latency is obtained by cut-through routing technique with sufficient communication bandwidth. The employment of an on-chip routing tab... View full abstract»

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  • A method to synthesize modular systolic arrays with local broadcast facility

    Publication Year: 1992, Page(s):415 - 428
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (628 KB)

    The author proposes a method to synthesize modular systolic arrays with local broadcast facility (i.e. arrays containing wires of length lower than a fixed -technology dependent- constant). The synthesis is made from a dependence graph which is not uniform but `locally broadcast'. This method aims at generalizing isolated results that have been recently reported on the acceleration of systolic alg... View full abstract»

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  • High speed bit-level pipelined architectures for redundant CORDIC implementation

    Publication Year: 1992, Page(s):358 - 372
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB)

    The CORDIC algorithm is well known as an efficient method for the computation of trigonometric/hyperbolic functions and vector rotations. The achievable throughput and the latency of CORDIC processors using conventional arithmetic are determined by the carry propagation occurring in additions/subtractions, since the CORDIC iterations are directed by the signs of intermediate results. Using a redun... View full abstract»

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  • Architecture and realization of a multi signal processor system

    Publication Year: 1992, Page(s):327 - 340
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    This paper describes a parallel distributed computer architecture called MUSIC (multi signal processor system with intelligent communication). A single processor element (PE) consists of a DSP 96002 from Motorola (60 MFlops), program and data memory and a fast, independent communication interface; all communication interfaces are connected through a communication ring. A system with 30 processor e... View full abstract»

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  • A transformative approach to the partitioning of processor arrays

    Publication Year: 1992, Page(s):4 - 20
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (740 KB)

    The paper describes the systematic design of processor arrays with a given dimension and a given number of processing elements. The unified approach to the solution of this problem called partitioning is based on the following concepts: (1) Algorithms and processor arrays are represented by (piecewise regular) programs. (2) The concept of stepwise refinement of programs is used to solve the partit... View full abstract»

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  • Linear scheduling is close to optimality

    Publication Year: 1992, Page(s):37 - 46
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    This paper deals with the problem of finding optimal schedulings for uniform dependence algorithms. Given a convex domain, let T f be the total time needed to execute all computations using the free (greedy) schedule and let Tl be the total time needed to execute all computations using the optimal linear schedule. The authors' main result is to bound ... View full abstract»

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  • Optimal design of lower dimensional processor arrays for uniform recurrences

    Publication Year: 1992, Page(s):636 - 648
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    The authors present a parameter-based approach for synthesizing systolic architectures from uniform recurrence equations. The scheme presented is a generalization of the parameter method proposed by G.J. Li and B.W. Wah (1985). The approach synthesizes optimal arrays of any lower dimension from a general uniform recurrence description of the problem. In other previous attempts for mapping uniform ... View full abstract»

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  • Associative information processing: algorithms and system

    Publication Year: 1992, Page(s):538 - 550
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (556 KB)

    Associative systems provide a flexibility ranging far beyond the scope of a conventional associative memory which simply provides a parallel search within a large amount of keywords to retrieve associated information. This paper presents several approaches to associative data processing. Algorithms are discussed that can easily be implemented or supported on an array computer. By means of dedicate... View full abstract»

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  • A projective geometry architecture for scientific computation

    Publication Year: 1992, Page(s):64 - 80
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    A large fraction of scientific and engineering computations involve sparse matrices. While dense matrix computations can be parallelized relatively easily, sparse matrices with arbitrary or irregular structure pose a real challenge to designers of highly parallel machines. A recent paper by N.K. Karmarkar (1991) proposed a new parallel architecture for sparse matrix computations based on finite pr... View full abstract»

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  • Compilation of narrowband spectral detection systems for linear MIMD machines

    Publication Year: 1992, Page(s):589 - 603
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    The author discusses the design of a program that maps a class of digital signal processing systems, called narrowband spectral detection systems, to linear MIMD machines. Such systems contain a mixture of data-parallel, systolic and purely serial computations. He describes a new technique, called geometric scheduling, that exploits the special features of the first two styles of computation, and ... View full abstract»

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  • Synthesis of application-specific multiprocessor systems including memory components

    Publication Year: 1992, Page(s):118 - 132
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (704 KB)

    Heterogeneous systems have the potential to achieve enhanced performance as well as cost-effectiveness over homogeneous systems when the application domain is known since they can match the problem structure more closely. It would be useful to have systematic methods for designing such systems for given applications. A formal design method, SOS, has been developed which can be used to synthesize o... View full abstract»

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  • Pipelining: just another transformation

    Publication Year: 1992, Page(s):163 - 175
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    A simple formulation of pipelining: `Pipelining with N stages is equivalent to retiming where the number of delays on all inputs or all outputs, but not both, is increased by N' is used as the basis for a convenient and efficient treatment of pipelining in design of application specific computers. Classification of pipelining according to the optimization goal (throughput and res... View full abstract»

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