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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 2 • Date Feb. 2014

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  • Table of contents

    Page(s): C1
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

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  • GASPAD: A General and Efficient mm-Wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm

    Page(s): 169 - 182
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (12686 KB) |  | HTML iconHTML  

    The design and optimization (both sizing and layout) of mm-wave integrated circuits (ICs) have attracted much attention due to the growing demand in industry. However, available manual design and synthesis methods suffer from a high dependence on design experience, being inefficient or not general enough. To address this problem, a new method, called general mm-wave IC synthesis based on Gaussian process model assisted differential evolution (GASPAD), is proposed in this paper. A medium-scale computationally expensive constrained optimization problem must be solved for the targeted mm-wave IC design problem. Besides the basic techniques of using a global optimization algorithm to obtain highly optimized design solutions and using surrogate models to obtain a high efficiency, a surrogate model-aware search mechanism (SMAS) for tackling the several tens of design variables (medium scale) and a method to appropriately integrate constraint handling techniques into SMAS for tackling the multiple (high-) performance specifications are proposed. Experiments on two 60 GHz power amplifiers in a 65 nm CMOS technology and two mathematical benchmark problems are carried out. Comparisons with the state-of-art provide evidence of the important advantages of GASPAD in terms of solution quality and efficiency. View full abstract»

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  • Biochip Synthesis and Dynamic Error Recovery for Sample Preparation Using Digital Microfluidics

    Page(s): 183 - 196
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (28438 KB) |  | HTML iconHTML  

    Recent advances in digital microfluidic biochips have led to a promising future for miniaturized laboratories, with the associated advantages of high sensitivity and reconfigurability. Since sample preparation plays an important front-end role in assays and laboratories in biochemical applications, and most of the analysis time is associated with sample collection, transportation, and preparation, it is important to minimize the time required for this key step in bioassays. Moreover, it is also critical to ensure the correctness of intermediate steps and recover from errors efficiently during sample preparation. We describe an optimization algorithm and the associated chip design method for sample preparation, including architectural synthesis and layout synthesis. We also present the first dynamic error recovery procedure for use during sample preparation. The proposed algorithm is evaluated on both real-life biochemical applications and synthetic test cases to demonstrate its effectiveness and efficiency. Compared to prior work, the proposed algorithm can achieve up to 50% reduction in sample preparation time, and the optimized chip layout can achieve over 40% reduction in sample preparation time. View full abstract»

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  • Performance-Driven Clustering of Asynchronous Circuits

    Page(s): 197 - 209
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (13224 KB) |  | HTML iconHTML  

    This paper proposes the method of generating asynchronous circuits from hardware description language specifications by clustering the synthesized gates into asynchronous pipeline stages while preserving liveness, meeting throughput and latency constraints, and minimizing area. This method provides a form of automatic pipelining in which the throughput of the overall design is not limited to the clock frequency or the level of pipelining in the original Register-Transfer Level (RTL) specification. The method is design-style agnostic and is thus applicable to many asynchronous design styles. View full abstract»

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  • Statistical Transistor-Level Timing Analysis Using a Direct Random Differential Equation Solver

    Page(s): 210 - 223
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7024 KB) |  | HTML iconHTML  

    To improve the accuracy of static timing analysis, the traditional nonlinear delay models are increasingly replaced by more physical gate models, such as current source models and transistor-level gate models. However, the extension of these accurate gate models for statistical timing analysis is still challenging. In this paper, we propose a novel statistical timing analysis method based on transistor-level gate models. The accuracy and efficiency are obtained by using an efficient random differential equation based solver. The correlations among signals and between input signals and delay are fully accounted for. In contrast to Monte Carlo simulation solutions, the variational waveforms for statistical delay calculation are obtained by simulating only once. At the end of statistical timing analysis, both the statistical delay moments and the variational waveforms are available. The proposed algorithm is verified with standard cells and ISCAS85 benchmark circuits in a 45-nm technology. The experimental results indicate that the proposed method can capture multiple input simultaneous switching for statistical delay calculation, and can provide 0.5% error for delay mean and 2.7% error for delay standard deviation estimation on average. The proposed statistical simulation introduces a small runtime overhead with respect to static timing analysis runtime. The MATLAB implementation of the proposed algorithm has two orders of magnitude speedup, compared to Spectre Monte Carlo simulation. View full abstract»

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  • Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs

    Page(s): 224 - 236
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (13245 KB) |  | HTML iconHTML  

    The flip-chip packaging is introduced for modern IC designs with higher integration density and larger I/O counts. It is necessary to consider routing obstacles for modern flip-chip designs, where the obstacles could be regions blocked for signal integrity protection (especially for analog/mixed-signal modules), prerouted or power/ground nets, and even for through-silicon vias for 3-D IC designs. However, no existing published works consider obstacles. To remedy this insufficiency, this paper presents the first work to solve the free-assignment flip-chip routing problem considering obstacles. For the free-assignment routing problem, most existing works apply the network-flow formulation. Nevertheless, we observe that no existing network-flow model can exactly capture the routability of a local routing region (tile) in presence of obstacles. This paper presents the first work that can precisely model the routability of a tile, even with obstacles. Based on this new model, a two-stage approach of global routing followed by detailed routing is proposed. The global routing computes a routing topology by the minimum-cost maximum-flow algorithm, and the detailed routing determines the precise wire positions. Dynamic programming is applied to further merge tiles to reduce the problem size. Compared to a state-of-the-art flow model with obstacle handling extensions, experimental results show that our algorithm can achieve 100% routability for all circuits while the extensions of the previous work cannot complete routing for any benchmark circuit with obstacles. View full abstract»

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  • On-Chip Codeword Generation to Cope With Crosstalk

    Page(s): 237 - 250
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (854 KB) |  | HTML iconHTML  

    Capacitive and inductive coupling between bus lines results in crosstalk induced delays. Many bus encoding techniques have been proposed to improve the performance. Existing implementation techniques and mapping algorithms in the literature only apply the specific encoding. This paper presents the first generalized framework for a stall-free on-chip codeword generation strategy that is scalable and easy to automate. It is applicable to the coupling aware encoding techniques that allow recursive codeword generation. The proposed implementation strategy iteratively generates codewords without explicitly enumerating them. Codeword mapping relies on graph-based representation that is unique to the given encoding technique. The codewords are calculated on-chip using basic function blocks, such as adders and multiplexers. Three encoding techniques were implemented using the proposed strategy. Experimental results show significant reduction in the area overhead and power dissipation over the existing method that uses random logic to implement the codec. View full abstract»

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  • Dynamic Indexing: Leakage-Aging Co-Optimization for Caches

    Page(s): 251 - 264
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (11285 KB) |  | HTML iconHTML  

    Traditional implementations of low-power states based on voltage scaling or power gating have been shown to have a beneficial effect on the aging phenomena caused by negative bias temperature instability (NBTI), which can be explained in terms of the intuitive correlation between the idleness and the reduced workload of a system. Such a joint benefit has been exploited only partially because of the different nature of energy and aging as cost functions: as a performance figure, aging is affected by the worst idleness pattern. Therefore, large potential energy savings usually result in limited aging reductions. In this paper, we address this problem in the context of power-managed caches, which represent a critical target for NBTI-reduced aging: given their symmetric structure, SRAM structures are, in particular, sensitive to NBTI effects because they cannot take advantage of the value-dependent recovery typical of NBTI. We propose a strategy called dynamic indexing, in which the cache indexing function is changed over time in order to uniformly distribute the idleness over all the various power managed units (e.g., lines). This distribution allows fully using the leakage optimization potential and extending the lifetime of a cache. We explore various alternatives, in particular different granularities of the power managed units as well as different reindexing functions. Experimental analysis shows that it is possible to simultaneously reduce leakage power and aging in caches, with minimal power consumption overhead. View full abstract»

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  • Cardio: CMP Adaptation for Reliability Through Dynamic Introspective Operation

    Page(s): 265 - 278
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (11292 KB) |  | HTML iconHTML  

    A modern digital system includes in a single chip many components: processing cores, large caches, memory controllers, and hardware accelerators. Looking forward, future semiconductor technologies will enable even higher device integration, overall increasing system performance while reducing energy consumption. Unfortunately, prominent experts agree that such technologies will be prone to both permanent and transient faults within their lifetime. With the goal of addressing this issue, we propose Cardio: a low-cost architecture for reliable chip multiprocessors. Our solution is based on a novel hardware/software co-design where silicon failures are detected in hardware and system reconfiguration is managed in software. Comparing Cardio with a state-of-the-art hardware-based resiliency solution, Immunet, we found that our design can achieve a comparable fault response time while requiring a much lower area overhead. The proposed solution relies on a distributed resource manager to collect information about a CMP component's health, and leverages a synchronized distributed control mechanism to recover from permanent failures. Such architecture can operate as long as at least one general-purpose processor is still functional. Our experimental evaluation indicates that the overall performance impact of Cardio is as low as 4.5%, and its dynamic reconfiguration time upon fault detection is comprised between 20 and 50 thousand cycles. View full abstract»

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  • Board-Level Functional Fault Diagnosis Using Multikernel Support Vector Machines and Incremental Learning

    Page(s): 279 - 290
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (16251 KB) |  | HTML iconHTML  

    Advanced machine learning techniques offer an unprecedented opportunity to increase the accuracy of board-level functional fault diagnosis and reduce product cost through successful repair. Ambiguous or incorrect diagnosis results lead to long debug times and even wrong repair actions, which significantly increase repair cost. We propose a smart diagnosis method based on multikernel support vector machines (MK-SVMs) and incremental learning. The MK-SVM method leverages a linear combination of single kernels to achieve accurate faulty-component classification based on the errors observed. The MK-SVMs thus generated can also be updated based on incremental learning, which allows the diagnosis system to quickly adapt to new error observations and provide even more accurate fault diagnosis. Two complex boards from industry, currently in volume production, are used to validate the proposed diagnosis approach in terms of diagnosis accuracy (success rate) and quantifiable improvements over previously proposed machine-learning methods based on several single-kernel SVMs and artificial neural networks. View full abstract»

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  • Path Predicate Abstraction for Sound System-Level Models of RT-Level Circuit Designs

    Page(s): 291 - 304
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2987 KB) |  | HTML iconHTML  

    A formal methodology for system verification of system-on-chip (SoC) designs is proposed. It ensures that system-level models are created that are sound abstractions of the concrete implementations at the register transfer level (RTL). For each SoC module at the RTL, an abstract description is obtained by path predicate abstraction. Path predicate abstraction is introduced based on the notion of operational graph coloring. It is shown to what extent the proposed abstraction mechanism is related to the notion of a stuttering bisimulation employed in the field of theorem proving. The proposed methodology, however, does not rely on theorem proving but is entirely based on standard techniques of property checking. Path predicate abstraction leads to time-abstract system models that can be composed into abstract system models. We demonstrate the practical feasibility of our approach by two comprehensive industrial case studies. View full abstract»

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  • Sequential Equivalence Checking for Clock-Gated Circuits

    Page(s): 305 - 317
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (10661 KB) |  | HTML iconHTML  

    Sequential logic synthesis often leads to substantially easier equivalence checking problems, compared to general-case sequential equivalence checking (SEC). This paper theoretically investigates when SEC can be reduced to a combinational equivalence checking (CEC) problem. It shows how the theory can be applied when sequential transforms are used, such as sequential clock gating, retiming, and redundancy removal. The legitimacy of such transforms is typically justified intuitively, by the designer or software developer believing that the two circuits reach the same state after a finite number of cycles, and no difference is observed at the outputs due to fanin non-controllability and fanout non-observability effects. View full abstract»

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  • Considering Crosstalk Effects in Statistical Timing Analysis

    Page(s): 318 - 322
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    The impact of crosstalk effects on timing performance is increasing as the device geometries are shrinking. As a consequence, crosstalk effects need to be considered in statistical timing analysis for higher accuracy. In this letter, the statistical interconnect delay due to crosstalk effects is calculated based on a piecewise linear delay change curve model (PLDM), which enables fast closed-form analytical delay evaluation. The PLDM-based method is independent of the delay change characteristics and is able to handle both Gaussian and non-Gaussian input skew distributions. The proposed method can be integrated into a statistical timing analyzer with runtime proportional to the number of samples for PLDM characterization. Experimental results demonstrate that the proposed method can estimate the delay mean and standard deviation for coupled RC interconnects at PTM 65-nm technology with errors better than -0.07% and -1.23%, respectively, with only 20 samples for PLDM characterization. In addition, the proposed method typically achieves two to three orders of magnitude speedup compared to Monte Carlo simulations. View full abstract»

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  • Unknown Output Values of Faulty Circuits and Output Response Compaction

    Page(s): 323 - 327
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5299 KB) |  | HTML iconHTML  

    When using output response compaction it is necessary to address the fact that circuits may produce unknown output values. Methods to address this issue ensure that the output response compactor would produce a unique fault-free signature that can be used for fault detection. This paper considers the unknown output values that are produced by faulty circuits. If a faulty circuit produces an unknown value when the output value of the fault-free circuit is known, the unknown faulty output value may affect the computation of a signature. The faulty signature may not be unique, and it may not always be different from a fault-free signature. The ability to verify that the fault will be detected based on its signature is thus lost. Without limiting the discussion to a particular output response compactor, the paper studies the prevalence of such faults in benchmark circuits, the prevalence of unknown faulty output values for which the corresponding fault-free values are known, and the effects of addressing this issue. View full abstract»

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  • Open Access

    Page(s): 328
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Page(s): C3
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors

    Page(s): C4
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu