15th Annual IEEE Symposium on High-Performance Interconnects (HOTI 2007)

22-24 Aug. 2007

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  • 15th Annual IEEE Symposium on High-Performance Interconnects - Cover

    Publication Year: 2007, Page(s): c1
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  • 15th Annual IEEE Symposium on High-Performance Interconnects - Title

    Publication Year: 2007, Page(s):i - iii
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  • 15th Annual IEEE Symposium on High-Performance Interconnects - Copyright

    Publication Year: 2007, Page(s): iv
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  • 15th Annual IEEE Symposium on High-Performance Interconnects - Table of contents

    Publication Year: 2007, Page(s):v - vii
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  • General Chairs' message

    Publication Year: 2007, Page(s): viii
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  • Program Chairs message

    Publication Year: 2007, Page(s): ix
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  • Steering Committee

    Publication Year: 2007, Page(s): x
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  • Organizing Committee

    Publication Year: 2007, Page(s): xi
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  • Technical Program Committee

    Publication Year: 2007, Page(s): xii
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  • CMOS Photonics - Bringing Moore's Law to Optical Interconnect

    Publication Year: 2007, Page(s): 3
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (139 KB) | HTML iconHTML

    Summary form only given. The acceleration of video as a key network application, combined with the scaling on-chip interconnect needs of multi-core processors, is driving the need for silicon-compatible high bandwidth low latency optical interconnect. CMOS photonics is a technology that seamlessly merges optics and electronics within production silicon chips, enabling a completely new generation o... View full abstract»

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  • On-Die Interconnect and Other Challenges for Chip-Level Multi-Processing

    Publication Year: 2007, Page(s): 4
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (144 KB)

    There is increasing interest in chip-level multi-processing, and in this talk I will discuss some the motivations, and some of the challenges in designing such chips. A key component is the on-die interconnect, and we will look at this along with some thoughts on core design, cache architecture, memory bandwidth, power management, error handling, and system scaling. View full abstract»

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  • Hands-on with the NetFPGA to build a Gigabit-rate Router

    Publication Year: 2007, Page(s):7 - 10
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (179 KB) | HTML iconHTML

    An open platform called the NetFPGA has been developed at Stanford University. The NetFPGA platform enables researchers and instructors to build high-speed, hardware-accelerated networking systems. The platform can be used in the classroom to teach students how to build Ethernet switches and Internet Prototcol (IP) routers using hardware rather than software. The platform can be used by researcher... View full abstract»

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  • Introduction to Programming High Performance Applications on the CELL Broadband Engine

    Publication Year: 2007, Page(s): 11
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB) | HTML iconHTML

    Summary form only given. Programming the STI CELL processor is about successfully exploiting its potential for delivering very high performance. The purpose of this tutorial is to give the programmer practical guidelines for achieving this goal. We begin by a brief overview of the main CELL architectural features and its software development environment. Then we discuss three basic aspects of CELL... View full abstract»

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  • Design of Interconnection Networks

    Publication Year: 2007, Page(s): 12
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (151 KB) | HTML iconHTML

    This paper focuses on future trends and challenges in interconnection network design. Historically used only in high-end supercomputers and telecom switches, interconnection networks are now found in systems of all sizes and all types from large supercomputers to small embedded systems-on-a-chip (SoC) and from inter-processor networks to router fabrics. Indeed, as system complexity and integration... View full abstract»

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  • Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects

    Publication Year: 2007, Page(s):15 - 20
    Cited by:  Papers (17)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (263 KB) | HTML iconHTML

    In modern multi-core system-on-chip (SoC) architectures, the design of innovative interconnection fabrics is indispensable. The concept of the network-on-chip (NoC) architecture has been proposed recently to better suit this requirement. Especially, the router architecture has a significant effect on the overall performance and energy consumption of the chip. We propose a dynamic path management s... View full abstract»

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  • Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing

    Publication Year: 2007, Page(s):21 - 28
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (253 KB) | HTML iconHTML

    A mesh of trees (MoT) on-chip interconnection network has been proposed recently to provide high throughput between memory units and processors for single-chip parallel processing (Balkan et al., 2006). In this paper, we report our findings in bringing this concept to silicon. Specifically, we conduct cycle-accurate Verilog simulations to verify the analytical results claimed in (Balkan et al., 20... View full abstract»

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  • Photonic NoC for DMA Communications in Chip Multiprocessors

    Publication Year: 2007, Page(s):29 - 38
    Cited by:  Papers (55)  |  Patents (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3525 KB) | HTML iconHTML

    As multicore architectures prevail in modern high- performance processor chip design, the communications bottleneck has begun to penetrate on-chip interconnects. With vastly growing numbers of cores and on-chip computation, a high-bandwidth, low-latency, and, perhaps most importantly, low-power communication infrastructure is critically required for next generation chip multiprocessors. Recent rem... View full abstract»

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  • Backlog Aware Low Complexity Schedulers for Input Queued Packet Switches

    Publication Year: 2007, Page(s):39 - 46
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (233 KB) | HTML iconHTML

    We study the problem of packet scheduling in input queued packet switches, with an emphasis on low complexity and ease of implementation. Toward this end, we propose a class of subset based schedulers, wherein an N x N switch is operated using only a small set of N configurations in every time-slot. We show that the performance of subset based scheduling is comparable to that of the benchmark maxi... View full abstract»

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  • Power Aware Management of Packet Switches

    Publication Year: 2007, Page(s):47 - 53
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB) | HTML iconHTML

    In this paper, we extend the idea of dynamic power management (DPM) to network packet switches, devices whose increasing speeds and densities are leading to costly and physically cumbersome power dissipation problems. In particular, we take a system-level approach, examining how operations in an input-queued (IQ) switch can be scheduled to balance power consumption on the one hand with average del... View full abstract»

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  • Implementation of Dynamic Bandwidth Re-allocation in Optical Interconnects using Microring Resonators

    Publication Year: 2007, Page(s):54 - 64
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (664 KB) | HTML iconHTML

    Dynamic bandwidth re-allocation (DBR) technique balances traffic by re-allocating bandwidth from under utilized links to over utilized links. This results in significant improvement in overall throughput and latency. In previous study, passive optical devices, namely arrayed waveguide gratings (AWGs) and couplers were used to implement DBR [2]. Although the performance was significantly improved, ... View full abstract»

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  • A Real-Time Worm Outbreak Detection System Using Shared Counters

    Publication Year: 2007, Page(s):65 - 72
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (212 KB) | HTML iconHTML

    New networking applications such as Network Intrusion Detection Systems (NIDS) require finding the frequently repeated strings in a packet stream for further investigation. The strategy of finding frequently repeated strings within a given time frame of the packet stream has been quite efficient to detect the polymorphic worms. A novel real-time worm outbreak detection system using two-phase hashi... View full abstract»

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  • Prototyping Fast, Simple, Secure Switches for Etha

    Publication Year: 2007, Page(s):73 - 82
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1604 KB) | HTML iconHTML

    We recently published our proposal for Ethane: A clean- slate approach to managing and securing enterprise networks. The goal of Ethane is to make enterprise networks (e.g. networks in companies, universities, and home offices) much easier to manage. Ethane is built on the premise that the only way to manage and secure networks is to make sure we can identify the origin of all traffic, and hold so... View full abstract»

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  • A Memory-Balanced Linear Pipeline Architecture for Trie-based IP Lookup

    Publication Year: 2007, Page(s):83 - 90
    Cited by:  Papers (31)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (473 KB) | HTML iconHTML

    Rapid growth in network link rates poses a strong demand on high speed IP lookup engines. Trie-based architectures are natural candidates for pipelined implementation to provide high throughput. However, simply mapping a trie level onto a pipeline stage results in unbalanced memory distribution over different stages. To address this problem, several novel pipelined architectures have been proposed... View full abstract»

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  • Building a RCP (Rate Control Protocol) Test Network

    Publication Year: 2007, Page(s):91 - 98
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (524 KB) | HTML iconHTML

    We recently proposed the Rate Control Protocol (RCP) as way to minimize download times (or flow-completion times). Simulations suggest that if RCP were widely deployed, downloads would frequently finish ten times faster than with TCP. This is because RCP involves explicit feedback from the routers along the path, allowing a sender to pick a fast starting rate, and adapt quickly to network conditio... View full abstract»

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  • ElephantTrap: A low cost device for identifying large flows

    Publication Year: 2007, Page(s):99 - 108
    Cited by:  Papers (17)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB) | HTML iconHTML

    This paper describes the design of ElephantTrap, a device which aims to cache the largest flows (the "elephants") on a network link. ElephantTrap differs from previous work on identifying large flows in one crucial sense: it does not attempt to accurately estimate the size of the flows it is trapping. This leads to an extremely lightweight design and a surprisingly good performance. ElephantTrap c... View full abstract»

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