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Proceedings., 11th IAPR International Conference on Pattern Recognition. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition,

Aug. 30 1992-Sept. 3 1992

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  • Proceedings. 11th IAPR International Conference on Pattern Recognition. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition

    Publication Year: 1992
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    Freely Available from IEEE
  • Parallel hypothesis verification

    Publication Year: 1992, Page(s):107 - 110
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (324 KB)

    The verification of identifying and pose hypotheses in model-based 3D object recognition systems can involve a time-consuming image rendering operation followed by pixel-level comparison of the input and rendered images. In situations where many such hypotheses need to be verified, exploitation of inherent data-parallelism between hypotheses and their corresponding object models can increase the e... View full abstract»

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  • SIBA: a VLSI systolic array chip for image processing

    Publication Year: 1992, Page(s):15 - 18
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    Describes the design and implementation of a two-dimensional systolic array processor for applications in image processing and computer vision. The processor architecture is based on a SIMD array of 4-bit processing elements, interconnected by a mesh network with four nearest neighbors. The PE array is programmable allowing the user to develop application-specific algorithms for performing analysi... View full abstract»

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  • Image recognition with an analog neural net chip

    Publication Year: 1992, Page(s):11 - 14
    Cited by:  Papers (1)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    The authors applied an analog neural net chip to several machine vision tasks, among them: locate the address blocks on mail pieces, find handwritten text on checks, and discriminate between handwritten and machine printed characters. The chip, operating as a co-processor of a workstation, provides a speed-up of about a factor of 1000, compared with the workstation. The computation speed achieved ... View full abstract»

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  • VLSI architecture for parallel concentration-contour approach

    Publication Year: 1992, Page(s):151 - 154
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (348 KB)

    A method called concentration-contour method is presented. It transforms a compound pattern into an integral one where contour analysis can be used. The concentration-contour method consists of four phases: (1) concentration of pattern, (2) extraction of contour, (3) transformation of numerical features, and (4) classification. The diagonal-diagonal regional projection transformation (DDRPT), whic... View full abstract»

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  • Generic functions for on-chip vision

    Publication Year: 1992, Page(s):1 - 10
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1056 KB)

    A smart retina is a device which intimately associates an optoelectronic layer with processing facilities. The rapprochement between acquisition and processing is particularly suited for the emergence of novel kinds of interaction, between analog and digital massive computations. Therefore, several attempts of analog, possibly neural, computations linked to the vision process are listed and discus... View full abstract»

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  • A real-time VLSI-based architecture for multi-motion estimation

    Publication Year: 1992, Page(s):147 - 150
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    This paper describes a new parallel architecture dedicated to multi-motion estimation. The input image is scanned by a standard video camera with 256 grey levels. Motion computing is based on the optical flow determination. Some constraints are proposed to allow multi-motion evaluation. The algorithm is presented and the main features of a 1-D systolic architecture which is based on a custom VLSI ... View full abstract»

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  • A scalable real-time image processing pipeline

    Publication Year: 1992, Page(s):142 - 146
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    To speed up image processing in the field of robot vision and industrial inspection, a pipeline element was made which is able to perform fast cellular logic operations. This Cellular Logic Processing Element (CLPE) is able to process binary images with a speed of 100 ns per pixel. The processing element is a CMOS VLSI-device which includes a Writable Logic Array for the storage of sets of 3×... View full abstract»

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  • A VLSI architecture for hierarchical scene matching

    Publication Year: 1992, Page(s):214 - 217
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (280 KB)

    Scene matching is the problem of matching regions of two images of the same scene taken by different sensors at different times or under different viewing conditions. Hierarchical scene matching generates a multiresolution pyramid of the images to be matched. The authors describe hierarchical scene matching technique, related work and their proposed VLSI architecture. They present a description of... View full abstract»

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  • Issues in parallel tree search for object recognition

    Publication Year: 1992, Page(s):225 - 228
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    The authors describe the parallel implementation of a 3D object recognition algorithm. The algorithm is representative of methods utilized by various computer vision researchers and presents some interesting problems that are generally overlooked by parallel processing researchers that have studied tree search problems. They describe their objectives in developing the parallel implementation and d... View full abstract»

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  • Parallel computation of 2-D wavelet transforms

    Publication Year: 1992, Page(s):111 - 114
    Cited by:  Papers (8)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (344 KB)

    Both from a mathematical as well as a biological perspective, wavelet transforms present a themselves as an attractive means for extracting low-level information from an image. The authors present a processor-time optimal algorithm to implement wavelet transforms on a VLSI implementable parallel digital architecture View full abstract»

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  • Implementing the Abingdon Cross benchmark on the ASP

    Publication Year: 1992, Page(s):91 - 94
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    The performance of the ASP computer on vision tasks has been evaluated by applying the Abingdon Cross benchmark using a number of different algorithms. In this paper, these algorithms are compared and contrasted on the basis of their performance View full abstract»

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  • Parallel stereo on fixed size arrays using zero crossings

    Publication Year: 1992, Page(s):79 - 82
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (272 KB)

    Presents a processor-time optimal partitioned implementation of a stereo matching algorithm using zero crossing points as matching primitives. The authors provide O(nm/P) time algorithm on √P×√P processor mesh array, where n is the number of zero crossing points in the left image, m is the set of possible candidate po... View full abstract»

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  • A miniaturized active vision system

    Publication Year: 1992, Page(s):58 - 61
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    The authors have developed a prototype miniaturized active vision system whose sensor architecture is based on a logarithmically structured space-variant pixel geometry. This system integrates a CCD sensor, miniature pan-tilt actuator, controller, general purpose processors and display. Due to the ability of space-variant sensors to cover large work-spaces yet provide high acuity with an extremely... View full abstract»

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  • Visual debugging for a pyramidal machine

    Publication Year: 1992, Page(s):137 - 141
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    This paper proposes a novel approach to program development for highly parallel architectures, primarily as far as debugging is concerned. The visual nature of the debugging stage, when dealing with image-processing algorithms, is heavily supported so that all the relevant information, which is generally either hidden or presented without its logical structures, is made available to programmers. T... View full abstract»

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  • A multilayer massively parallel architecture for optical flow computation

    Publication Year: 1992, Page(s):209 - 213
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    A two-layers architecture for optical flow computation is presented, which uses neural nets in the lower layer and a special relaxation system in the upper layer. The high degree of parallelism of the architecture makes it particularly suitable for real-time applications View full abstract»

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  • An analog CMOS programmable and configurable neural network

    Publication Year: 1992, Page(s):222 - 224
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    The object of this paper is to describe an analog CMOS realization of a programmable and configurable neural network chip and the mixed-mode analog/digital system it will be used in. The intention is that the chip(s) be used in the environment of a digital host computer, with the training or learning algorithm implemented in software, while also permitting operation in a stand-alone execution phas... View full abstract»

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  • Parallel quadtree representation and moment invariants computation of binary image for hierarchical matching on pyramid machine

    Publication Year: 1992, Page(s):87 - 90
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Quadtree region representation, image properties computation of binary image and moment invariants are implemented on a pyramid machine. Based on those algorithms a parallel pattern recognition technique is proposed. Exploiting the parallel quadtree representation on pyramid machine, moment invariants seems to be a good descriptor in a hierarchical coarse-fine matching strategy. For a particular i... View full abstract»

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  • A VLSI hardware accelerator for dynamic time warping

    Publication Year: 1992, Page(s):27 - 30
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (268 KB)

    Describes an area and time efficient systolic array architecture for computations in Dynamic Time Warping (DTW). The special purpose architecture is used to perform the band matrix multiplication in order to compute the local distance metric based on Itakura's log likelihood distance. The time complexity of the algorithm is O(nk) where n and k are the number of elements in the row of the first and... View full abstract»

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  • Rank order filtering on SIMD machines

    Publication Year: 1992, Page(s):75 - 78
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    Rank order filters form an important class of low level image operations that have widespread applications in image smoothing, texture analysis, etc. In the paper, the authors study several ways of computing rank order filters on processor array architectures. They also present a replicated data algorithm for efficient processing of small images on relatively large processor arrays. Results of imp... View full abstract»

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  • Proteus: a reconfigurable computational network for computer vision

    Publication Year: 1992, Page(s):43 - 54
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1244 KB)

    The Proteus architecture is a highly parallel MIMD, multiple instruction, multiple-data machine, optimized for large granularity tasks such as machine vision and image processing. The system can achieve 20 Giga-flops (80 Giga-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/second. The system employs a hierarchical reconfigurable interconnection network with ... View full abstract»

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  • Flexible real-time programming of a distributed transputer-based vision system

    Publication Year: 1992, Page(s):133 - 135
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    The authors describe the major aspects in their transputer-based automatic vision system (TAVS) aiming to implement a scaleable and easily reconfigurable system, in which the mapping of image processing and recognition algorithms to the hardware is facilitated by automatic code generation schemes, separating methodic design and implementation details. The paper presents the system design and under... View full abstract»

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  • An integrated approach to real-time pattern recognition

    Publication Year: 1992, Page(s):177 - 180
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    This paper details the architecture and design of a VLSI CMOS retina dedicated to very fast pattern recognition. The implementation of the recognition algorithms into silicon are detailed. The performances of the ixj pixel retina are evaluated for various input pattern sizes. A 64×32 pixel integrated circuit design is presented which performs a pattern recognition and localisation in less th... View full abstract»

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  • Efficient implementation of neural networks on the DREAM machine

    Publication Year: 1992, Page(s):204 - 208
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    High-throughput implementations of neural networks are needed in order to expand the use of this technology from small research problems into practical `real-world' applications. Due to the wide range of possible neural network paradigms and the rapid evolution of these models, high degree of implementation flexibility if essential. The Dynamically Reconfigurable Extended Array Multiprocessor (DRE... View full abstract»

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  • The wavelet transform-a CMOS VLSI ASIC implementation

    Publication Year: 1992, Page(s):19 - 22
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Describes a complementary metal oxide semiconductor (CMOS) very large scale integration (VLSI) application specific integrated circuit (ASIC) implementation of the wavelet transform. This custom hardware can provide higher speed, in the order of 5-50 million data samples/sec (needed for video applications) and/or lower power (needed for battery powered applications) than software implementations o... View full abstract»

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